SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 148

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.2
Transfer Request Generation
DMAC supports two types of request generation method: internal and external. In either request
generation mode, once a DMA channel is started, a DMA request causes the DMAC to arbitrate for the
bus and begin transferring data.
A DMA request must be issued for the DMAC to initiate a data transfer. Each DMA channel in the
Internal Request Generation
request generation mode, a transfer request is generated as soon as the Str bit in the CCRn is set.
no transition to a higher-priority DMA channel or a bus master occurs, the channel will use 100%
of the available bus bandwidth to transfer all data continuously.
External Request Generation
request generation mode, setting the Str bit in the CCRn puts the channel in Ready state. While in
Ready state, assertion of the INTDREQn signal (where n is the channel number) coming from the
Interrupt Controller (INTC) causes a transfer request to be generated. Externally generated requests
support data transfers from memory to memory and between memory and an I/O peripheral.
CCRn. However, in the TMP1940CYAF, INTDREQn is an active-low, level-sensitive signal.
Therefore, the PosE bit must be cleared to 0.
programmed in the TrSize field in the CCRn. The transfer size can be 32 bits, 16 bits or 8 bits.
number). DACKn is asserted: 1) when an I/O peripheral bus cycle has completed and 2) when the
Byte Count Register (BCRn) has reached zero in memory-to-memory transfer. Consequently, a
memory-to-I/O or I/O-to-memory transfer request terminates after one DMA bus cycle completes,
whereas memory-to-memory transfer can continuously move large blocks of data in response to a
single DMA request.
must be noted that, even if that happens, a DMA bus cycle might be executed after the interrupt
request has been cleared.
A channel is programmed for internal request by clearing the ExR bit in the CCRn. In internal
An internally generated request keeps a transfer request pending until the transfer is complete. If
Internally generated requests support only memory-to-memory transfer.
A channel is programmed for external request by setting the ExR bit in the CCRn. In external
INTDREQn can be programmed for either edge or level sensitivity through the PosE bit in the
The transfer size, i.e., the amount of data to be transferred in response to a transfer request, is
A transfer request is removed by assertion of the DACKn signal (where n is the channel
The INTC might clear INTDREQn before the DMAC accepts it and begins a data transfer. It
TMP1940CYAF-106
TMP1940CYAF