SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 269

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. Analog-to-Digital Converter (ADC)
AN3/ ADTRG (P53)
converter (ADC).
general-purpose digital inputs (Port 5) if not needed as analog channels.
AN7 (P57)
AN6 (P56)
AN5 (P55)
AN4 (P54)
AN2 (P52)
AN1 (P51)
AN0 (P50)
The TMP1940CYAF has a 8-channel, multiplexed-input, 10-bit successive-approximation ananlog-to-digital
Figure 15.1 shows a block diagram of the ADC. The eight analog input channels (AN0–AN7) can be used as
Note:
VREFH
VREFL
Ensure that the ADC has halted before executing an insturction to place the TMP1940CYAF in IDLE,
SLEEP or STOP mode to reduce power supply current. Otherwise, the TMP1940CYAF might go into a
standby mode while the internal analog comparator is still active. In SLOW mode, the ADC must be
disabled.
(ADMOD1)
A/D Mode Control Register 1
Channel Selection
Control Circuit
ADCH[2:0]
Internal Data Bus
VREFON
Figure 15.1 ADC Block Diagram
ADTRGE
TMP1940CYAF-227
Sample-and-
Hold
EOCF
end
A/D Mode Control Register 0 (ADMOD0)
ADBF
busy
D/A Converter
Internal Data Bus
ITM0
Comparator
interrupt
A/D Converter Control
REPEAT SCAN ADS
repeat
Circuit
scan
TMP1940CYAF
start
Interrupt
Request
(INTAD)
(ADREG04H–37H)
(ADREG04L–37L)
ADTRG
Result Registers
A/D Conversion
Internal Data Bus