SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 70

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input:
Output: Pin direction is output.
PU*:
P00–07
P10–17
P20–27
P30 ( RD ), P31 ( WR )
P32–37
P40–43
P44 (SCOUT)
P50–57
P70–76
P77 (INT0)
P80–87
P90–95
P96 (XT1) – P97 (XT2)
PA0–PA3
PA4–PA7
ALE
AM0, AM1
X1
X2
NMI
RESET
:
Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and output-only
pins assume the high-Impedance state.
The input gate is active; the input voltage must be held at either the high or low level to keep the input pin from
floating.
Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in high-impedance
state.
Pins
Input pin
Input mode
Output mode
AD0–AD7
Input mode
Output mode
AD8–AD15
Input mode
Output mode, A0–A7/A16–A23
Output pin
Input mode
Output mode
Input mode
Output mode
Input mode
Output mode
Input pin
Input mode
Output mode
Input mode
Output mode
Input mode (INT0)
Input mode
Output mode
Input mode
Output mode
Input mode
Output mode
XT1, XT2
Input mode
Output mode
Input mode (INT1–INT4)
Input mode
Output mode
Output pin
Input pin
Input pin
Input pin
Output pin
Table 5.8 Pin States in STOP Mode
Input/Output
TMP1940CYAF-28
SYSCR2.DRVE
Output High
Output Low
Input
Input
Input
Input
Input
PU*
PU*
PU*
PU*
0 SYSCR2.DRVE
TMP1940CYAF
Output High
Output Low
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
1