SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 250

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.8
14.5.9
14.5.10 Lost-Arbitration Detection Monitor
SCL Bus Line
Internal SDA Level
(Master A)
Internal SDA Level
(Master B)
SDA Bus Line
Asserting and Deasserting Interrupt Requests
cleared to 0. While the PIN bit is 0, the SBI pulls the SCL line low.
In transmitter mode, the PIN bit is subsequently set to 1 each time the SBI0DBR is written. In receiver
mode, the PIN bit is set to 1 each time the SBI0DBR is read.
and the received slave address matches the value in the I2C0CR or is all 0s (i.e., a general call).
SBI Operating Modes
SBI for I
condition while the bus is busy loses bus arbitration, with no START condition occurring on the SDA
and SCL lines.
of Master A and Master B are the same. At point a Master B’s internal data level makes a low-to-high
transition while Master A’s internal data level remains at logic low. However, the SDA bus line is held
low because it is the wired-AND of the two data outputs. When the SCL bus clock goes high at point b,
the addressed slave device reads the data transmitted by Master A (i.e., winning master). Master B loses
arbitration and switches off its data output stage, releasing its SDA line (high), so that it does not affect
the data transfer initiated by the winning master.
procedure continues with the second data word.
When an SBI interrupt (INTS2) is generated, the Pending Interrupt Not (PIN) bit in the SBI0CR2 is
After transmission or reception of one data word on the I
It takes a period of t
In Address Recognition mode (ALS=0), the PIN bit is cleared when the SBI is addressed as a slave
A write of 1 by software sets the PIN bit, but a write of 0 has no effect on this bit.
The SBIM[1:0] field in the SBI0CR2 is used to select an operating mode of the SBI. To configure the
A switch to Port mode should only be attempted when the bus is free.
The I
A master may start a transfer only if the bus is free. A master that attempts to generate a START
The I
Figure 14.11 shows the arbitration procedure for two masters. Up until point a, the internal data levels
In case two competing masters have transmitted exactly the same first data word, the arbitration
2
2
C bus is a multi-master bus and has an arbitration procedure to ensure correct data transfers.
C-bus arbitration takes place on the SDA line.
2
C Bus mode, set the SBIM[1:0] field to 10.
Figure 14.11 Arbitration Procedure of Two Masters
LOW
for the SCL line to be released after the PIN bit is set.
TMP1940CYAF-208
a
b
2
Master B loses arbitration and
connects a high output level to the bus.
C bus, the PIN bit is automatically cleared.
TMP1940CYAF