SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 279

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3 Programming Examples
Converting the analog input voltage on the AN3 pin to a digital value and storing the converted value in
a memory location (0xFFFF_B800) using an A/D interrupt (INTAD) handler routine
Converting the analog input voltages on AN0–AN2 sequentially in channel scan continuous conversion
mode
X = Don't care
Notes:
Settings in the main routine
IMCEHH
ADMOD1
ADMOD0
Interrupt routine processing example
r4
r4
(FFFFB800H)
IMCEHH
ADMOD1
ADMOD0
The ADC supports both polled and interrupt-driven operation. The CPU can perform polling
operation to detect completion of a conversion.
fadc: A/D conversion clock selected by the ADCCLK register
Don’t poll the ADRxRF bit in the ADREGxxL register.
In single conversion modes, poll the ADBF bit in the ADMOD0.
In any conversion modes, the EOCF bit in the ADMOD0 can be polled. After the EOCF bit is
set, one or two fadc clocks are required as shown below before the ADREGxH/L can be
read.
Fixed-channel single conversion mode
Fixed-channel continuous conversion mode
Channel scan single scan conversion mode
Channel scan continuous conversion mode
> > 6
7 6 5 4 3 2 1 0
X X 0 1 0 1 0 0
1 X X X 0 0 1 1
X X 0 0 0 0 0 1
X X 0 1 0 0 0 0
1 X X X 0 0 1 1
X X 0 0 0 0 0 1
ADREG37
r4
Conversion Mode
TMP1940CYAF-237
Enables INTAD and sets its priority level to 4.
Selects AN3 as the analog input channel.
Starts conversion in fixed-channel single conversion mode.
Loads the conversion result into general-purpose register r4 from
ADREG37L and ADREG37H.
Shifts the contents of r4 six bits to the right, padding 0s to the
vacated MSB bits.
Stores the contents of r4 to address 0xFFFF_B800.
Disables INTAD.
Selects AN0–AN2 as analog input channels.
Starts conversion in channel scan continuous conversion mode.
Time Required Before Reading the ADREGxx
2 fadc clocks
2 fadc clocks
1 fadc clock
1 fadc clock
TMP1940CYAF