SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 183

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.2
12.2.3
Up-Counter (UC0)
TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either one of three prescalar
outputs (
selected through the programming of the TB0CLK[1:0] field in the TB0MOD register.
UC0 is cleared to 0000H, if so enabled, when it reaches the value in the TB0RG1H/L register. The
TB0CLE bit in the TB0MOD register allows the user to enable and disable this clearing. If it is
disabled, the UC0 acts as a free-running counter.
Timer Registers (TB0RG0H/L and TB0RG1H/L)
reaches the time constant value in each timer register, the associated comparator block generates a
match-detect signal.
instruction or a series of two byte-store instructions. When byte-store instructions are used, the low-
order byte must be stored first, followed by the high-order byte. The 16-bit timer registers are often
simply referred to as TB0RG0 and TB0RG1 without the H and L suffix.
enabled and disabled through the programming of the TB0RDE bit in the TB0RUN: 0=disable,
1=enable.
buffer. This takes place when a match is detected between the UC0 and the TB0RG1.
valid values before the timer can be used. A reset clears the TB0RUN.TB0RDE bit to 0, disabling the
double-buffering function. To use this function, the TB0RUN.TB0RDE bit must be set to 1 after
loading the TB0RG0 and TB0RG1 with time constants. When TB0RUN.TB0RDE=1, the next time
constant can be written to the register buffer.
Note:
Note 1: The TB0RG0 and the corresponding register buffer are mapped to the same address (0xFFFF_F188
Note 2: Programming the TB0RDE bit should only be attempted when the timer is not running.
The TMRB0 contains a 16-bit binary up-counter, which is driven by a clock selected by the
The TB0RUN bit in the TB0RUN register is used to start the UC0 and to stop and clear the UC0. The
An overflow interrupt (INTTBOF0) is generated upon a counter overflow.
Each timer channel has two 16-bit timer registers containing a time constant. When the up-counter
Each of the timer registers (TB0RG0H/L, TB0RG1H/L) can be written with either a halfword-store
One of the two timer registers, TB0RG0, is double-buffered. The double-buffering function can be
If double-buffering is enabled, the TB0RG0 latches a new time constant value from the register
Upon reset, the contents of the TB0RG0 and TB0RG1 are undefined; thus, they must be loaded with
The following diagram shows the addresses of each timer register.
Programming the TB0CLK[1:0] and TB0CLE bits in the TB0MOD register should only be attempted
when the timer is not running.
thru 0xFFFF_F189). When TB0RUN.TB0RDE=0, a time constant value is written to both the TB0RG0
and the register buffer; when TB0RUN.TB0RDE=1, a time constant value is written only to the
register buffer. Therefore, the double-buffering function should be disabled when writing an initial
time constant to the timer register.
T4, T16) or the external clock applied to the TB0IN0 pin. The clock input can be
TMP1940CYAF-141
TMP1940CYAF