AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 83

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below V
the LVPECL driver. In this case, VS_DRV on the AD9520
should equal V
combination shown results in a dc bias point of VS_DRV − 2 V,
the actual common-mode voltage is VS_DRV − 1.3 V because
there is additional current flowing from the AD9520 LVPECL
driver through the pull-down resistor.
The circuit is identical for the case where VS_DRV = 2.5 V, except
that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually
turned on or off and set as inverting or noninverting. These
outputs are 3.3 V or 2.5 V CMOS compatible. However, every
output driver (including the LVPECL drivers) must be run at
either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and
3.3 V outputs.
Figure 70. DC-Coupled 3.3V LVPECL Far-End Thevenin Termination
VS_DRV
LVPECL
Figure 72. AC-Coupled LVPECL with Parallel Transmission Line
VS_DRV
VS_DRV
LVPECL
LVPECL
200Ω
Figure 71. DC-Coupled 3.3 V LVPECL Y-Termination
S
of the receiving buffer. Although the resistor
0.1nF
0.1nF
(NOT COUPLED)
SINGLE-ENDED
200Ω
Z
Z
0
0
TRANSMISSION LINE
100Ω DIFFERENTIAL
50Ω
50Ω
= 50Ω
= 50Ω
(COUPLED)
127Ω
83Ω
VS_DRV
50Ω
100Ω
50Ω
50Ω
127Ω
83Ω
V
S
= VS_DRV
LVPECL
LVPECL
V
S
LVPECL
V
S
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of
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When single-ended CMOS clocking is used, some of the
following guidelines apply.
Point-to-point connections should be designed such that each
driver has only one receiver, if possible. Connecting outputs in
this manner allows for simple termination schemes and minimizes
ringing due to possible mismatched impedances on the output
trace. Series termination at the source is generally required to
provide transmission line matching and/or to reduce current
transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
signal integrity.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9520 do not supply enough current
to provide a full voltage swing with a low impedance resistive, far-
end termination, as shown in Figure 74. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9520 offers LVPECL outputs
that are better suited for driving long traces where the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
Figure 74. CMOS Output with Far-End Termination
CMOS
Figure 73. Series Termination of CMOS Output
CMOS
10Ω
10Ω
MICROSTRIP
50Ω
(1.0 INCH)
60.4Ω
V
S
100Ω
100Ω
CMOS
CMOS
AD9520-3