ADF4360-9BCPZ Analog Devices Inc, ADF4360-9BCPZ Datasheet - Page 18

• Manufacturer Part Number: ADF4360-9BCPZ
• Description: Synthesizer And VCO
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-9BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 5mA
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 1.1 to 400MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4360-9
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N counter
latch during power-down, the part locks at the correct frequency
because the part is already in the correct frequency band. The
lock time depends on the value of capacitance on the C
which is <15 ms for 10 μF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 μs.
The N counter value cannot be changed while the part is in
power-down because the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Figure 23
shows the input data format for programming the control latch.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded in PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When a power-down is activated (either
synchronous or asynchronous mode), the following events occur:
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•
•
•
•
•
•
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
N
pin,
Rev. A | Page 18 of 24
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1. CPI6, CPI5, and CPI4 determine Current
Setting 2 (see the truth table in Figure 23).
Output Power Level
Bit PL1 and Bit PL2 set the output power level of the VCO (see
the truth table in Figure 23).
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360 family is the mute-
till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit (DB9) puts the charge pump into three-state mode
when programmed to a 1. For normal operation, it should be
set to 0.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.
DIVOUT Control
The on-chip multiplexer is controlled by D3, D2, and D1 (see
the truth table in Figure 23).
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The
recommended setting is 5 mA. The 7.5 mA setting is
permissible in some applications (see the truth table in Figure 23).