Synthesizer And VCO

ADF4360-9BCPZ

Manufacturer Part NumberADF4360-9BCPZ
DescriptionSynthesizer And VCO
ManufacturerAnalog Devices Inc
TypeFanout Distribution, Integer N Synthesizer (RF)
ADF4360-9BCPZ datasheet
 


Specifications of ADF4360-9BCPZ

PllYesInputCMOS
OutputClockNumber Of Circuits1
Ratio - Input:output1:2Differential - Input:outputNo/No
Frequency - Max400MHzDivider/multiplierYes/No
Voltage - Supply3 V ~ 3.6 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case24-LFCSP
Frequency-max400MHzNumber Of Elements1
Supply Current5mAPll Input Freq (min)10MHz
Pll Input Freq (max)250MHzOperating Supply Voltage (typ)3.3V
Operating Temp Range-40C to 85CPackage TypeLFCSP EP
Output Frequency Range1.1 to 400MHzOperating Supply Voltage (min)3V
Operating Supply Voltage (max)3.6VOperating Temperature ClassificationIndustrial
Pin Count24Lead Free Status / RoHS StatusLead free / RoHS Compliant
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ADF4360-9
CURRENT
SETTING 2
DB23
DB22
DB21
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
RSV
RSV
PD2
PD1
CPI6
CPI5
CPI4
CPI6
CPI5
CPI3
CPI2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
PL2
0
0
1
1
CE PIN
PD2
PD1
MODE
0
X
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
1
1
1
SYNCHRONOUS POWER-DOWN
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
OUTPUT
CURRENT
POWER
SETTING 1
LEVEL
DB9
CPI3
CPI2
CPI1
PL2
PL1
MTLD
CPG
CP
CPI4
I
(mA)
CP
CPI1
4.7kΩ
0
0.31
1
0.62
0
0.93
1
1.25
0
1.56
CP
1
1.87
0
0
2.18
1
1
2.50
CP GAIN
CPG
0
CURRENT SETTING 1
1
CURRENT SETTING 2
MUTE-TIL-LOCK DETECT
MTLD
0
DISABLED
1
ENABLED
PL1
OUTPUT POWER LEVEL
CURRENT USING TUNED LOAD
USING 50Ω TO V
0
3.5mA
–9dBm
–19dBm
1
5.0mA
–6dBm
–15dBm
0
7.5mA
–3dBm
–12dBm
1
11.0mA
0dBm
–9dBm
Figure 23. Control Latch
Rev. A | Page 14 of 24
CORE
DIVOUT
POWER
CONTROL
LEVEL
DB8
DB7
DB6
DB5
DB4
DB3
DB2
PDP
D3
D2
D1
CR
PC2
PC1
C2 (0) C1 (0)
PC2
CORE POWER LEVEL
PC1
0
0
2.5mA
0
5mA (RECOMMENDED)
1
1
0
7.5mA
1
1
10mA
PHASE DETECTOR
PDP
POLARITY
COUNTER
0
NEGATIVE
CR
OPERATION
1
POSITIVE
0
NORMAL
1
R, A, B COUNTERS
CHARGE PUMP
HELD IN RESET
OUTPUT
NORMAL
THREE-STATE
D3
D2
D1
MUXOUT
0
0
0
DV
DD
VCO
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
1
0
N DIVIDER OUTPUT
0
1
1
DV
DD
R DIVIDER OUTPUT
1
0
0
A CNTR/2 OUT
1
0
1
A CNTR OUT
1
1
0
DGND
1
1
1
CONTROL
BITS
DB1
DB0