ADF4360-9BCPZ Analog Devices Inc, ADF4360-9BCPZ Datasheet - Page 7

Synthesizer And VCO

ADF4360-9BCPZ

Manufacturer Part Number
ADF4360-9BCPZ
Description
Synthesizer And VCO
Manufacturer
Analog Devices Inc
Type
Fanout Distribution, Integer N Synthesizer (RF)r
Datasheet

Specifications of ADF4360-9BCPZ

Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
400MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-LFCSP
Frequency-max
400MHz
Number Of Elements
1
Supply Current
5mA
Pll Input Freq (min)
10MHz
Pll Input Freq (max)
250MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
LFCSP EP
Output Frequency Range
1.1 to 400MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2
AV
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
DD
should be placed as close as possible to this pin. AV
3, 8, 11, 22
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
4
RF
A
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
OUT
description of the various output stages.
5
RF
B
VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
OUT
Matching section for a description of the various output stages.
6
V
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
VCO
should be placed as close as possible to this pin. V
7
V
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
TUNE
output voltage.
9
L1
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10
L2
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12
C
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
C
13
R
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
SET
synthesizer. The nominal voltage potential at the R
I
= 11.75/R
CPmax
For example, R
14
C
Internal Compensation Node. This pin must be decoupled to V
N
15
DGND
Digital Ground.
16
REF
Reference Input. This is a CMOS input with a nominal threshold of V
IN
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20
DIVOUT
This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21
DV
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
DD
be placed as close as possible to this pin. DV
23
LD
Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24
CP
Charge Pump Output. When enabled, this provides ±I
internal VCO.
PIN 1
CPGND
1
INDICATOR
18 DATA
17 CLK
AV
2
DD
ADF4360-9
16 REF
AGND
3
15 DGND
RF
A
4
TOP VIEW
OUT
RF
B
5
14 C
(Not to Scale)
OUT
N
V
6
13 R
VCO
SET
Figure 3. Pin Configuration
must have the same value as DV
DD
must have the same value as AV
VCO
pin is 0.6 V. The relationship between I
SET
SET
= 4.7 kΩ and I
= 2.5 mA.
SET
CPmax
must have the same value as AV
DD
CP
Rev. A | Page 7 of 24
ADF4360-9
IN
.
DD
.
DD
and R
CP
with a 10 μF capacitor.
VCO
/2 and a dc equivalent input resistance of
DD
.
DD
to the external loop filter, which in turn drives the
is
SET

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