EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 153

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Introduction
Overview
Altera Corporation-Preliminary
March 2007
CIII51003-1.0
Two key factors affecting board design today drove the design of
Cyclone III devices I/O capabilities. The first is the diversification of I/O
standards in many low-cost applications. The second is a significant
increase in the required I/O performance. Our objective was to create a
device that made accommodating these design needs easy and flexible.
Cyclone III I/O flexibility has been increased from previous generation
low-cost FPGAs by allowing all I/O standards to be selected on all I/O
banks. Improvements to on-chip termination (OCT) support and by
adding dedicated differential buffers, eliminate the need for external
resistors in many applications, such as display system interfaces. The
Altera
planning features that allow you to plan and optimize I/O system
designs even before the design files are available.
Each Cyclone III device I/O pin is fed by an I/O element (IOE) located at
the ends of logic array block (LAB) rows and columns around the
periphery of the Cyclone III device. The I/O pins support various single-
ended and differential I/O standards. Each IOE contains a bidirectional
I/O buffer and five registers for registering input, output, and output-
enable signals. Cyclone III I/O supports a wide range of features:
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Single-ended non-voltage-referenced and voltage-referenced I/O
standards
Differential I/O standards
Output current strength control
Programmable slew rate control
Open-drain outputs
Bus-hold circuitry
PCI-clamp diode
Programmable pull-up resistors in user mode
Programmable input and output delays
Programmable low-voltage differential signaling (LVDS)
pre-emphasis
On-chip termination with and without calibration
®
Quartus
®
II software completes the solution with powerful pin
7. Cyclone III Device I/O
Features
Preliminary
7–1