EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 306

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
JTAG
Configuration
10–70
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
t
t
t
f
t
t
t
CH
CL
CLK
MAX
CD2UM
C D 2 C U
C D 2 U M C
Table 10–13. FPP Timing Parameters for Cyclone III Devices (Part 2 of 2)
Symbol
This information is preliminary.
This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
Table
DCLK
DCLK
DCLK
DCLK
CONF_DONE
CONF_DONE
CONF_DONE
CLKUSR
10–13:
f
high time
low time
frequency
period
option on
high to user mode
high to
high to user mode with
Parameter
For more information about device configuration options and how to
create configuration files, refer to the Software Settings section in volume
2 of the Configuration Handbook.
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, a microprocessor can control the
transfer of configuration data from a storage device, such as flash
memory, to the target Cyclone III device.
All information in
External Host” on page 10–62
microprocessor as an external host. Refer to that section for all
configuration and timing information.
JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on PCBs with tight lead spacing. The BST architecture
can test pin connections without using physical test probes and capture
functional data while a device is operating normally. You can also use the
JTAG circuitry to shift configuration data into the device. The Quartus II
software automatically generates SRAM Object Files that can be used for
JTAG configuration with a download cable in the Quartus II software
programmer.
CLKUSR
enabled
(3)
“FPP Configuration Using a MAX II Device as an
t
CLKUSR
C D 2 C U
4 × maximum
DCLK
is also applicable when using a
Min
300
3.2
3.2
7.5
+ (3,180 ×
period
period)
Altera Corporation-Preliminary
Note (1)
Max
133
650
March 2007
Units
MHz
ns
ns
ns
µs