EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 61

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
See
page 4–25
Address Clock Enable Support
All Cyclone III memory blocks support address clock enable, which holds
the previous address value for as long as the signal is enabled and
addressstall is active high (addressstall = '1'). When you
configure the memory blocks in dual-port mode, each port has its own
independent address clock enable.
Figure 4–3
register output feeds back to its input via a multiplexer. The multiplexer
output is selected by the address clock enable (addressstall) signal.
Figure 4–3. Cyclone III Address Clock Enable Block Diagram
The address clock enable is typically used for cache memory applications
to improve efficiency during a cache-miss. The default value for the
address clock enable signals is low (disabled).
the address clock enable waveforms during read and write cycles,
respectively.
“Single-Port Mode” on page 4–10
addressstall
address[0]
address[N]
for more information.
shows an address clock enable block diagram. The address
clock
Cyclone III Device Handbook, Volume 1
and
address[0]
address[N]
register
register
“Single-Clock Mode” on
Figures 4–4
address[0]
address[N]
and
4–5
Overview
show
4–7