EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 229

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III
Memory
Interfaces
Features
Figure 9–6. Cyclone III DDR Input Registers
Altera Corporation-Preliminary
March 2007
dataout_h
dataout_l
Cyclone III memory interfaces, including DDR input registers, DDR
output registers, on-chip termination, and PLLs, are discussed below.
DDR Input Registers
The DDR input registers are implemented with three internal logic
element (LE) registers for every DQ pin. These LE registers are located in
the logic array block (LAB) adjacent to the DDR input pin.
illustrates the Cyclone III DDR input registers.
The DDR data is first fed to two registers, input register A
register B
■
■
■
The sync_reg_h and sync_reg_l registers accept the data from the
DDR input registers, then transfer the data to a FIFO to synchronize the
two data streams to the rising edge of the system clock. Since the
read-capture clock is generated by the PLL, the read-data strobe signal
(DQS or CQ) is not used during read in Cyclone III devices. Hence,
postamble is not a concern in this case.
sync_reg_h
sync_reg_l
Register
Register
LE
LE
Input register A
edge of the clock
Input register B
edge of the clock
Register C
clock
I
.
I
aligns the data before it is synchronized with the system
Register C
Register
DDR Input Registers in Cyclone III
LE
I
I
captures the DDR data present during the falling
captures the DDR data present during the rising
I
Input Register A
Input Register B
neg_reg_out
Cyclone III Device Handbook, Volume 1
Cyclone III Memory Interfaces Features
Register
Register
LE
LE
I
I
Capture Clock
I
Figure 9–6
and input
PLL
DQ
9–15