EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 163

no-image

EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
Datasheets

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F256I7N
Manufacturer:
IR
Quantity:
14 520
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA31
Quantity:
214
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA
Quantity:
90
Part Number:
EP3C16F256I7N
Manufacturer:
XILINX
0
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA
0
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP3C16F256I7N
0
Altera Corporation-Preliminary
March 2007
f
f
Cyclone III devices can interface to 3.3 V systems using 3.3 V and 3.0 V
I/O standards by following a few simple guidelines. For more
information, refer to AN 447: Interfacing Cyclone III Devices with
3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
Slew Rate Control
The output buffer for each Cyclone III device I/O pin provides optional
programmable output slew-rate, with three settings for each supported
I/O standard: slow, medium, and fast. The default slew rate is the fastest
setting. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slower slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Since
each I/O pin has an individual slew-rate control, you can specify the slew
rate on a pin-by-pin basis. The slew-rate control affects both the rising and
falling edges. Slew rate control is available for single-ended I/O
standards with current strength 8 mA or higher. 3.3-V LVTTL and 3.3-V
LVCMOS I/O standards do not support slew rate control.
Refer to the Assignment Editor chapter in volume 2 of the Quartus II
Handbook for more information about how to set the slew rate feature.
Open-Drain Output
Cyclone III devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (for example, interrupt
and write-enable signals) that can be asserted by multiple devices in your
system.
Note to
(1)
(2)
SSTL-2 Class I
SSTL-2 Class II
Table 7–1. Programmable Current Strength
The default setting in the Quartus II software is 50 Ω OCT with calibration for all
non-voltage reference and HSTL/SSTL class I/O standards. The default setting
is 25 Ω OCT without calibration for HSTL/SSTL class II I/O standards.
The default current setting in the Quartus II software is highlighted in italic bold
for 3.3-V LVTTL and 3.3-V LVCMOS I/O standard.
I/O Standard
Table
7–1:
Top and Bottom I/O Pins
I
OH
/I
OL
Cyclone III Device Handbook, Volume 1
12
16
8
Current Strength Setting (mA)
(1)
(Part 3 of 3)
Left and Right I/O Pins
I/O Element Features
12
16
8
7–11

Related parts for EP3C16F256I7N