EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 331

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
DEV_OE
DEV_CLRn
TDI
TDO
Pin Name User Mode Pin Type
Table 10–22. Optional Configuration Pins (Part 2 of 2)
Table 10–23. Dedicated JTAG Pins (Part 1 of 2)
Pin Name
N/A
N/A
N/A if option is on.
I/O if option is off.
N/A if option is on.
I/O if option is off.
User Mode
Input
Output
Table 10–23
stable before and during configuration to prevent accidental loading of
JTAG instructions. The TDI and TMS have weak internal pull-up resistors,
while TCK has a weak internal pull-down resistor. If you plan to use the
SignalTap
JTAG pins of the Cyclone III device to a JTAG header on your board.
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of
supply.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to V
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of
not being shifted out of the device. The
bank 1. For recommendations on connecting a JTAG chain with multiple
voltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG)
Boundary Scan Testing for Cyclone III Devices chapter in the Cyclone III
Device Handbook.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by leaving this pin unconnected.
Input
Input
®
Pin Type
II Embedded Logic Array Analyzer, you need to connect the
describes the dedicated JTAG pins. JTAG pins must be kept
Optional pin that allows the user to override all
tri-states on the device. When this pin is driven low, all
I/O pins are tri-stated; when this pin is driven high, all
I/O pins behave as programmed. This pin is enabled
by turning on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
Optional pin that allows you to override all clears on
all device registers. When this pin is driven low, all
registers are cleared; when this pin is driven high, all
registers behave as programmed. This pin is enabled
by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.
Description
TCK
Cyclone III Device Handbook, Volume 1
C C
. The
.
TDO
TCK
TDI
Description
pin is powered by V
. The pin is tri-stated if data is
pin is powered by the V
Device Configuration Pins
C C I O
in I/O
10–95
C C I O