WM8976GEFL/V Wolfson Microelectronics, WM8976GEFL/V Datasheet - Page 2

Audio CODECs Mono ADC Stereo DAC with Spkr

WM8976GEFL/V

Manufacturer Part Number
WM8976GEFL/V
Description
Audio CODECs Mono ADC Stereo DAC with Spkr
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8976GEFL/V

Mounting Style
SMD/SMT
Package / Case
QFN-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WM8976
DESCRIPTION ....................................................................................................... 1
FEATURES ............................................................................................................ 1
APPLICATIONS ..................................................................................................... 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION .......................................................................................... 4
ORDERING INFORMATION .................................................................................. 4
PIN DESCRIPTION ................................................................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................ 6
RECOMMENDED OPERATING CONDITIONS ..................................................... 6
ELECTRICAL CHARACTERISTICS ..................................................................... 7
SPEAKER OUTPUT THD VERSUS POWER ...................................................... 10
POWER CONSUMPTION .................................................................................... 11
AUDIO PATHS OVERVIEW ................................................................................ 13
SIGNAL TIMING REQUIREMENTS .................................................................... 14
INTERNAL POWER ON RESET CIRCUIT .......................................................... 18
DEVICE DESCRIPTION ...................................................................................... 20
REGISTER MAP .................................................................................................. 85
DIGITAL FILTER CHARACTERISTICS ............................................................ 102
APPLICATION INFORMATION ......................................................................... 109
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TERMINOLOGY .............................................................................................................. 9
SYSTEM CLOCK TIMING ............................................................................................. 14
AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 14
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................. 15
CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 16
CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 17
INTRODUCTION ........................................................................................................... 20
INPUT SIGNAL PATH ................................................................................................... 22
ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 28
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ............................................ 32
OUTPUT SIGNAL PATH ............................................................................................... 44
3D STEREO ENHANCEMENT ...................................................................................... 51
ANALOGUE OUTPUTS ................................................................................................. 51
DIGITAL AUDIO INTERFACES ..................................................................................... 66
AUDIO SAMPLE RATES ............................................................................................... 71
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 71
COMPANDING .............................................................................................................. 73
GENERAL PURPOSE INPUT/OUTPUT ........................................................................ 75
OUTPUT SWITCHING (JACK DETECT)....................................................................... 76
CONTROL INTERFACE ................................................................................................ 77
RESETTING THE CHIP ................................................................................................ 78
POWER SUPPLIES ....................................................................................................... 79
RECOMMENDED POWER UP/DOWN SEQUENCE .................................................... 80
POWER MANAGEMENT .............................................................................................. 84
REGISTER BITS BY ADDRESS ................................................................................... 87
TERMINOLOGY .......................................................................................................... 102
DAC FILTER RESPONSES ........................................................................................ 103
ADC FILTER RESPONSES ........................................................................................ 103
HIGHPASS FILTER ..................................................................................................... 104
5-BAND EQUALISER .................................................................................................. 105
TABLE OF CONTENTS
PD Rev 4.4 July 2009
Production Data
2

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