WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 20

• Manufacturer Part Number: WM9713LGEFL/RV
• Description: Audio CODECs Stereo AC'97 CODEC T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9713LGEFL/RV

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 8 KSPs
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9713L
CLOCK GENERATION
CLOCK DIVISION MODES
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WM9713L supports clocking from 2 separate sources, which can be selected via the AC’97 interface:
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The source clock is divided to appropriate frequencies in order to run the AC’97 interface, PCM
interface, voice DAC and Hi-fi DSP by means of a programmable divider block. Clock rates may be
changed during operation via the AC’97 link in order to support alternative modes, for example low
power mode when voice data is being transmitted only. A PLL is present to add flexibility in selection
of input clock frequencies, typical choices being 2.048MHz, 4.096MHz or 13MHz.
INITIALISING THE AC’97 LINK
By default, the AC’97 link is disabled and therefore will not be running after power on or a COLD
reset event. Before any register map configuration can begin, it is necessary to start the AC’97 link.
This is achieved by sending a WARM reset to the CODEC as defined in Figure 6.
Default mode on power-up also assumes a clock will be present on MCLKA with the PLL powered
down. After a WARM reset the CODEC will start the AC’97 link using MCLKA as a reference. This
enables data to be clocked via the AC’97 link to define the desired clock divider mode and whether
PLL needs to be activated.
Note: MCLKA can be any available frequency.
When muxing between MCLKA and MCLKB both clocks must be active for at least two clock cycles
after the switching event.
Figure 10 shows the clocking strategy for WM9713L. Clocking is controlled by CLK_MUX, CLK_SRC
and S[6:0].
The registers used to set these switches can be accessed from register address 44h (see Table 3).
If a mode change requires switching from an external clock to a PLL generated clock then it is
recommended to set the clock division ratios required for the PLL clock scheme prior to switching
between clocks. This option is accommodated by means of two sets of registers. S
set the divide ratio of the clock when in PLL mode and S
derived from an external source. If the PLL is selected (CLK_SRC = 0), S[6:0] = S
is defined in register 46h (see Table 4) and is written to using the page address mode. More details
on page address mode for controlling the PLL are found on page 20. Register 46h also contains a
number of separate control bits relating to the PLL’s function. If an external clock is selected
(CLK_SRC = 1) S[6:0] = S
44h and 46h enables pre-programming of the required clock mode before the PLL output is selected.
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External clock input MCLKA
External clock input MCLKB
CLKAX2, CLKBX2 – clock doublers on inputs MCLKA and MCLKB.
CLK_MUX - selects between MCLKA and MCLKB.
CLK_SRC – selects between external or PLL derived clock reference.
S[3:0] – sets the voice DAC clock rate and PCM interface clock when in master mode
(division ratio 1 to 16 available).
S[6:4] - sets the hi-fi clocking rate (division ratio 1 to 8 available).
EXT
[6:0]. S
EXT
[6:0] is defined in register address 44h. Writing to registers
EXT
[6:0] is used to divide the clock when it is
PP Rev 3.2 September 2008
PLL
PLL
[6:0] is used to
Pre-Production
[6:0]. S
PLL
[6:0]
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