WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 25

Audio CODECs Stereo AC'97 CODEC T/P Interface

WM9713LGEFL/RV

Manufacturer Part Number
WM9713LGEFL/RV
Description
Audio CODECs Stereo AC'97 CODEC T/P Interface
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM9713LGEFL/RV

Number Of Adc Inputs
1
Number Of Dac Outputs
1
Conversion Rate
8 KSPs
Interface Type
AC97
Resolution
12 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Minimum Operating Temperature
- 25 C
Number Of Channels
1 ADC, 1 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM9713LGEFL/RV
Manufacturer:
WOLFSON
Quantity:
20 000
Pre-Production
w
PLL REGISTER PAGE ADDRESS MAPPING
The clock division control bits S
register 46h using a sub-page address system. The 3 bit pager address allows 8 blocks of 4 bit data
words to be accessed whilst the register address is set to 46h. This means that when register
address 46h is selected a further 7 cycles of programming are required to set all of the page data
bits. Control bit allocation for these page addresses is described in Table 6.
Table 6 Pager Control Bit Allocation
Powerdown for the PLL and internal clocks is via registers 26h and 3Ch (see Table 7).
Table 7 PLL Powerdown Control
111
110
101
100
011
010
001
000
26h
3Ch
N.B. both PR5 and PLL must be asserted low before PLL is enabled
REGISTER
ADDRESS
ADDRESS
PAGE
31:28
27:24
23:22
21:20
19:16
15:12
11:8
7:4
3:0
13
9
BIT
BIT
S
S
Reserved
K[21:0]
PR5
PLL
PLL
PLL
LABEL
LABEL
[6:4]
[3:0]
PLL
[6:0] and the PLL fractional N division bits are accessed through
0h
0h
0h
0h
0h
0h
0h
0h
0h
1 (Off)
1 (Off)
DEFAULT
DEFAULT
Clock division control bus S
divider reads this control word if PLL is
enabled. Bits [6:4] and [3:0] have the same
functionality as 44h [14:12] and [11:8]
respectively
Reserved bits
Sigma Delta Modulator control word for
fractional N division. Division resolution is
1/22
Internal Clock Disable Control
1 = Disabled
0 = Enabled
PLL Disable Control
1 = Disabled
0 = Enabled
2
DESCRIPTION
DESCRIPTION
PP Rev 3.2 September 2008
PLL
WM9713L
[6:0]. Clock
25

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