WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 32

• Manufacturer Part Number: WM9713LGEFL/RV
• Description: Audio CODECs Stereo AC'97 CODEC T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9713LGEFL/RV

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 8 KSPs
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9713L
AUDIO ADCS
STEREO ADC
w
The WM9713L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high
quality audio recording at low power consumption. The ADC sample rate can be controlled by writing
to a control register (see “Variable Rate Audio”). It is independent of the DAC sample rate.
To save power, the left and right ADCs can be separately switched off using the Powerdown bits
ADCL and ADCR (register 3Ch, bits 5:4), whereas PR0 disables both ADCs (see “Power
Management” section). If only one ADC is running, the same ADC data appears on both the left and
right AC-Link slots.
The output from the ADC can be sent over either the AC link as usual, or output via the PCM
interface which may be configured on the GPIO pins.
HIGH PASS FILTER
The WM9713L audio ADC incorporates a digital high pass filter that eliminates any DC bias from the
ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by
writing a ‘1’ to the HPF bit (register 5Ch, bit 3).
This high pass filter corner frequency can be selected to have different values in WM9713L, to suit
applications such as voice where a higher cutoff frequency is required.
Table 9 Controlling the ADC Highpass Filter
ADC SLOT MAPPING
By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the
right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by
setting the ASS (ADC slot select) control bits as shown below.
Table 10 ADC Slot Mapping
5Ch
5Ah
Note: the filter corner frequency is proportional to the sample rate.
5Ch
Additional
Functions
(2)
REGISTER
REGISTER
ADDRESS
ADDRESS
3
5:4
1:0
BIT
BIT
HPF
HPMODE
ASS
LABEL
LABEL
00
DEFAULT
0
00
DEFAULT
ADC Data Slot Mapping Control
00 =
01 =
10 =
11 =
ADC HPF Disable Control
0 = HPF enabled (for audio)
1 = HPF disabled (for DC measurements)
HPF Cut-Off Control
00 = 7Hz @ fs=48kHz
01 = 82Hz @ fs=16kHz
10 = 82Hz @ fs=8kHz
11 = 170Hz @ fs=8kHz
Left Data
Slot 10
Slot 3
Slot 7
Slot 6
DESCRIPTION
DESCRIPTION
PP Rev 3.2 September 2008
Right Data
Pre-Production
Slot 11
Slot 4
Slot 8
Slot 9
32