WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 26

• Manufacturer Part Number: WM9713LGEFL/RV
• Description: Audio CODECs Stereo AC'97 CODEC T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9713LGEFL/RV

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 8 KSPs
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9713L
DIGITAL INTERFACES
AC97 INTERFACE
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The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface.
The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and
RESETB) and is the sole control interface with access to all data streams on the device except for
the Voice DAC. The PCM interface is available through the GPIO pins (PCMCLK, PCMFS, PCMDAC
and PCMADC) and provides access to the Voice DAC. It can also transmit the data from the Stereo
ADC. This can be useful, for example, to allow both sides of a phone conversation to be recorded by
mixing the transmit and receive paths on one of the ADC channels and transmitting it over the PCM
interface.
INTERFACE PROTOCOL
The WM9713L uses an AC’97 interface for both data transfer and control. The AC-Link has 5 wires:
Figure 12 AC-Link Interface (typical case with BITCLK generated by the AC97 codec)
The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed data streams (slots 0
to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total
of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive
multiple data streams (e.g. audio, touchpanel, AUXDAC, control) at sample rates up to 48kHz.
Detailed information can be found in the AC’97 (Revision 2.2) specification, which can be obtained at
www.intel.com/design/chipsets/audio/
Note:
SDATAOUT and SYNC must be held low when RESETB is applied. These signals must be held low
for the entire duration of the RESETB pulse and especially during the low-to-high transition of
RESETB. If SDATAOUT or SYNC is high during reset, the WM9713L may enter test modes.
Information relating to this operation is available in the AC'97 specification or in Wolfson applications
note WAN-0104 available at www.wolfsonmirco.com.
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SDATAIN (pin 8) carries data from the WM9713L to the controller
SDATAOUT (pin 5) carries data from the controller to the WM9713L
BITCLK (pin 6) is a clock, derived from either MCLKA or MCLKB inputs and
supplied to the controller.
SYNC is a synchronization signal generated by the controller and passed to the
WM9713L
RESETB resets the WM9713L to its default state
PP Rev 3.2 September 2008
Pre-Production
26