WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 37

Audio CODECs Stereo AC'97 CODEC T/P Interface

WM9713LGEFL/RV

Manufacturer Part Number
WM9713LGEFL/RV
Description
Audio CODECs Stereo AC'97 CODEC T/P Interface
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM9713LGEFL/RV

Number Of Adc Inputs
1
Number Of Dac Outputs
1
Conversion Rate
8 KSPs
Interface Type
AC97
Resolution
12 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Minimum Operating Temperature
- 25 C
Number Of Channels
1 ADC, 1 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM9713LGEFL/RV
Manufacturer:
WOLFSON
Quantity:
20 000
Pre-Production
w
When operating in stereo, the peak detector takes the maximum of left and right channel peak
values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is
preserved. However, the ALC function can also be enabled on one channel only. In this case, only
one PGA is controlled by the ALC mechanism, while the other channel runs independently with its
PGA gain set through the control register.
When one ADC channel is unused, the peak detector disregards that channel. The ALC function can
also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are
mixed to mono in the analogue domain, before entering the ADCs.
Table 14 ALC Control
62h
ALC / Noise
Gate Control
60h
ALC Control
REGISTER
ADDRESS
15:14
13:11
10:9
15:12
11:8
7:4
3:0
BIT
ALCSEL
MAXGAIN
ZCTIMEOUT
ALCL
HLD
DCY
ATK
LABEL
00
(OFF)
111
(+30dB)
11
1011
(-12dB)
0000
(0ms)
0011
(192ms)
0010
(24ms)
DEFAULT
ALC Function Channel Control
00 = ALC disabled
01 = ALC on right channel only
10 = ALC or left channel only
11 = ALC on both left and right channels
ALC PGA Gain Limit Control
000 = -12dB
… (6dB steps)
111 = +30dB
ALC Zero Cross Timeout Delay
Control
00 = 2
01 = 2
10 = 2
11 = 2
Note: Timeout delay values shown
when BITCLK=12.288MHz
ALC Target Level Control
0000 = -28.5dBFS
… (1.5dB steps)
1111 = -6dBFS
Note: This is the target signal level at
the ADC input
ALC Hold Time Control
0000 = 0ms
0001 = 2.67ms
… (time doubles with every step)
1111 = 43.691s
ALC Decay Time Control
0000 = 24ms
… (time doubles with every step)
1010 to 1111 = 24.58s
ALC Attack Time Control
0000 = 6ms
… (time doubles with every step)
1010 to 1111 = 6.14s
14
15
16
17
x t
x t
x t
x t
BITCLK
BITCLK
BITCLK
BITCLK
DESCRIPTION
PP Rev 3.2 September 2008
(1.33ms)
(2.67ms)
(5.33ms)
(10.67ms)
WM9713L
37

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