WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet - Page 23

• Manufacturer Part Number: WM9713LGEFL/RV
• Description: Audio CODECs Stereo AC'97 CODEC T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9713LGEFL/RV

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 8 KSPs
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-Production
PLL MODE
w
The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation:
The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz –
19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1). Through use of a clock divider (div by 2 / 4)
on the input to the PLL frequencies up to 78.6MHz can be accommodated. The input clock divider is
enabled by DIVSEL (0=Off) and the division ratio is set by DIVCTL (0=div2, 1=div4).
Figure 11 PLL Architecture
Table 4 PLL Clock Control
46h
REGISTER
ADDRESS
•
•
Integer N
Fractional N
15:12
11
10
9
8
6:4
3:0
BIT
N[3:0]
LF
SDM
DIVSEL
DIVCTL
PGADDR
PGDATA
LABEL
0000
0 = off
0 = off
0 = off
0
000
0000
DEFAULT
PLL N Divide Control
0000 = Divide by 1
0001 = Divide by 1
0010 = Divide by 2
…
1111 = Divide by 15
Note: must be set between 05h and 0Ch for
integer N mode
PLL Low Frequency Input Control
1 = Low frequency mode (input clock <
8.192MHz)
0 = Normal mode
PLL SDM Enable Control
1 = Enable SDM (required for fractional N
mode)
0 = Disable SDM
PLL Input Clock Division Control
0 = Divide by 1
1 = Divide according to DIVCTL
PLL Input Clock Division Value Control
0 = Divide by 2
1 = Divide by 4
Pager Address
Pager address bits to access programming
of K[21:0] and S
Pager Data
Pager data bits
DESCRIPTION
PLL
PP Rev 3.2 September 2008
[6:0]
WM9713L
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