DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 144

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DS33Z11

Manufacturer Part Number
DS33Z11
Description
Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33Z11

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 10-5 MII Transmit Functional Timing
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing
Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is
2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation. RX_DV is asserted by the PHY from the first
nibble of the preamble in 100 Mbps operation or first nibble of SFD for 10 Mbps operation. The data on RXD[3:0]
is not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode). RX_ERR should be tied low
when in DCE Mode.
Figure 10-7 MII Receive Functional Timing
In RMII Mode, TX_EN is high with the first bit of the preamble. The TXD[1:0] is synchronous with the 50 MHz
REF_CLK. For 10 Mbps operation, the data bit outputs are updated every 10 clocks.
Figure 10-8 RMII Transmit Interface Functional Timing
TXD[1:0]
TXD[3:0]
TX_EN
TX_EN
REF_CLK
COL
TX_CLK
CRS
RX_CLK
RXD[3:0]
TX_CLK
TXD[3:0]
TX_EN
P
P
R
R
P
P
E
E
R
A
A
R
M
M
E
B
B
E
L
L
A
E
E
A
J
E
E
J
144 of 172
J
M
M
J
J
B
B
J
L
J
L
J
E
E
F
F
F
C
C
C
S
S
S

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