DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 19

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RX_CRS/
CRS_DV
RX_CLK
RX_DV
TX_EN
RXD[0]
RXD[1]
RXD[2]
RXD[3]
TXD[0]
TXD[1]
TXD[2]
TXD[3]
NAME
DS33Z11
CSBGA
PIN #
(169)
C11
D11
D10
E10
A10
B11
A11
B9
C9
D9
E9
C8
DS33ZH1
BGA(100)
PIN #
D10
C10
B10
A10
D9
C9
C8
B6
A8
B7
B8
A9
1
TYPE
IO
O
O
I
I
I
19 of 172
Transmit Enable (MII): This pin is asserted high when
data TXD [3:0] is being provided by the DS33Z11. The
signal is deasserted prior to the first nibble of the next
frame. This signal is synchronous with the rising edge
TX_CLK. It is asserted with the first bit of the preamble.
Transmit Enable (RMII): When this signal is asserted, the
data on TXD [1:0] is valid. This signal is synchronous to
the REF_CLK.
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is
the least significant bit of the data. When TX_EN is low
the data on TXD should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD
[1:0] presented synchronously with the rising edge of
REF_CLK.
Receive Clock (MII): Timing reference for RX_DV,
RX_ERR and RXD[3:0], which are clocked on the rising
edge. RX_CLK frequency is 25 MHz for 100 Mbps
operation and 2.5 MHz for 10 Mbps operation. In DTE
mode, this is a clock input provided by the PHY. In DCE
mode, this is an output derived from REF_CLK providing
2.5 MHz (10 Mbps operation) or 25 MHz (100 Mbps
operation).
Receive Data 0 through 3(MII): Four bits of received
data, sampled synchronously with the rising edge of
RX_CLK. For every clock cycle, the PHY transfers 4 bits
to the DS33Z11. RXD[0] is the least significant bit of the
data. Data is not considered valid when RX_DV is low.
Receive Data 0 through 1(RMII): Two bits of received
data, sampled synchronously with REF_CLK with 100
Mbps Mode. Accepted when CRS_DV is asserted. When
configured for 10 Mbps Mode, the data is sampled once
every 10 clock periods.
Receive Data Valid (MII): This active high signal indicates
valid data from the PHY. The data RXD is ignored if
RX_DV is not asserted high.
Receive Carrier Sense (MII): Should be asserted (high)
when data from the PHY (RXD[3:0) is valid. For each
clock pulse 4 bits arrive from the PHY. Bit 0 is the least
significant bit. In DCE mode, connect to V
Carrier Sense/Receive Data Valid (RMII): This signal is
asserted (high) when data is valid from the PHY. For each
clock pulse 2 bits arrive from the PHY. In DCE mode, this
signal must be grounded.
FUNCTION
DD
.