DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 23

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MODEC[0]
MODEC[1]
DCEDTES
HWMODE
RMIIMIIS
FULLDS
NAME
H10S
DS33Z11
CSBGA
PIN #
(169)
A13
B10
D5
D6
D7
C4
A9
DS33ZH1
BGA(100)
PIN #
A3
A4
—
—
—
—
—
1
TYPE
I
I
I
I
I
I
23 of 172
Hardware Mode: Connect to V
Hardware Mode. MODEC[1:0] determines the default
hardware setting to be used. This pin must be held low for
control by a microprocessor or an external EEPROM.
Mode Control:
Software Mode Options (HWMODE = 0)
00 = Read/Write Strobe Used (Intel Mode)
01 = Data Strobe Used (Motorola Mode)
10 –SPI Master Mode (External EEPROM)
11- Reserved. Do not use.
Hardware Mode Options (HWMODE = 1)
00 = Default Hardware Mode. See
01 = Reserved. Do not use.
10 = Hardware Mode for T3/E3 rates. See
11 = Reserved. Do not use.
Note that in the 100-pin CSBGA (DS33ZH11) package,
only MODEC[1] is available to the user. MODEC[0] is
internally connected to V
DCE or DTE Selection: The user must set this pin high
for DCE Mode selection or low for DTE Mode. This input
affects operation in both software and hardware mode. In
DCE Mode, the DS33Z11 MAC port can be directly
connected to another MAC. In DCE Mode, the Transmit
clock (TX_CLK) and Receive clock (RX_CLK) are output
by the DS33Z11.
Note that there is no software bit selection of DCEDTES.
Note that DCE Mode is only relevant when the MAC
interface is in MII mode.
RMII or MII Selection: Set high to configure the MAC for
RMII interfacing. Set low for MII interfacing. This pin is tied
low in the 100 pin CSBGA (DS33ZH11) package option.
Full Duplex Selection (Hardware Mode): When in
Hardware Mode, this pin must be set to 1 for proper
operation (Full Duplex Mode). In software mode, this pin
has no effect and duplex selection is controlled in the
SU.GCR register. This pin is tied high in the 100 pin
CSBGA (DS33ZH11) package option.
100Mb/10Mb (Hardware Mode): When in Hardware
Mode, this pin selects the packet PHY data rate. Set high
for 100 Mbps. Set low for the MII/RMII interface to run at
10 Mbps. In the software mode this pin has no effect and
the rate selection is controlled in the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to V
FUNCTION
SS
.
DD
.
DD
to place the device in
Table
8-8.
Table
8-8.