DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 74

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, MCLK configuration, and BPCLK configuration. These registers are preserved to provide
code compatibility with the multiport devices in this product family. The global registers bit descriptions are
presented below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: ID07 Reserved for future use
Bit 6: ID06 Reserved for future use
Bit 5: ID05 If this bit is set the device contains a RMII interface
Bit 4: ID04 If this bit is set the device contains a MII interface
Bit 3: ID03 If this bit is set the device contains an Ethernet PHY
Bits 0-2: ID00-ID02 A three-bit count that is equal to 000b for the first die revision, and is incremented with each
successive die revision. May not match the two-letter die revision code on the top brand of the device.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 5-7: ID13-15 Number of ports in the device minus 1. (i.e. 000 = 1 port)
Bit 4: ID12 If this bit is set the device has LIU functionality
Bit 3: ID11 If this bit is set the device has a framer
Bit 2: ID10 Reserved for future use
Bit 1: ID09 If this bit is set the device has HDLC or X.86 encapsulation
Bit 0: ID08 If this bit is set the device has inverse multiplexing functionality
ID07
ID15
7
0
7
0
ID06
ID14
6
0
6
0
GL.IDRL
Global ID Low Register
00h
GL.IDRH
Global ID High Register
01h
ID05
ID13
5
1
5
0
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ID04
ID12
4
1
4
0
ID03
ID11
3
0
3
0
ID02
ID10
2
0
2
0
ID01
ID09
1
0
1
1
ID00
ID08
0
0
0
0