DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 40

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.12 Flow Control
Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z11
allows for optional flow control based on the queue high watermark or through host processor intervention. There
are 2 basic mechanisms that are used for flow control:
Note that the terms “transmit queue” and “receive queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
The following flow control options are possible:
Note that in order to use flow control, the receive queue size (in AR.RQSC1) must be 02h or greater. The receive
queue high threshold (in SU.RQHT) must be set to 01h or greater, but must be less than the queue size. If the
high threshold is set to the same value as the queue size, automatic flow control will not be effective. The high
threshold must always be set to less than the corresponding queue size.
The following table provides all the options on flow control mechanism for DS33Z11.
Table 8-4 Options for Flow Control
Configuration
HWMODE Pin
AFCS Pin
ATFLOW Bit
JAME Bit
FCB Bit
(Pause)
FCE Bit
Pause Timer
•
•
•
•
•
In half duplex mode, a jam sequence is sent that causes collisions at the far end. The collisions cause the
transmitting node to reduce the rate of transmission.
In full duplex mode, flow control is initiated by the receiving node sending a pause frame. The pause
frame has a timer parameter that determines the pause timeout to be used by the transmitting node.
Automatic flow control can be enabled in hardware mode by the AFCS pin.
Automatic flow control can be enabled in software mode with the SU.GCR.ATFLOW bit. Note that the
user does not have control over SU.MACFCR.FCE and FCB bits if ATFLOW is set. The mechanism of
sending pause or jam is dependent only on the receive queue high threshold.
Manual flow control can be performed through software when SU.GCR.ATFLOW = 0. The host processor
must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR.FCE bits.
Full duplex,
No flow
control
N/A
N/A
N/A
N/A
N/A
HARDWARE MODE
1
0
Automatically
With respect
to SU.RQHT
Set to AFCS
Flow control
Full duplex,
Set to 140h
Controlled
pin = High
N/A
N/A
1
1
Controlled By
Controlled By
Manual Flow
Half Duplex;
Control
User
User
N/A
N/A
N/A
0
0
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Automatically
Automatically
Flow Control
Half Duplex;
Automatic
Controlled
Controlled
N/A
N/A
N/A
SOFTWARE MODE
0
1
Controlled By
Controlled by
Programmed
Manual Flow
Full Duplex;
by User
Control
User
User
N/A
N/A
0
0
Automatically
Automatically
Programmed
Flow Control
Full Duplex;
Automatic
Controlled
Controlled
by User
N/A
N/A
0
1