DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 20

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COL_DET
A0/BREO
RX_ERR
A1/SCD
NAME
MDIO
MDC
DS33Z11
CSBGA
PIN #
(169)
B13
C12
C13
B12
A1
B1
revision to
revision to
DS33ZH1
Potential
Potential
BGA(100)
add on
ball A5
add on
ball D8
PIN #
future
future
B9
—
—
—
1
TYPE
IO
MICRO PORT/SPI
O
—
I
I
I
20 of 172
Receive Error (MII): Asserted by the MAC PHY for one or
more RX_CLK periods indicating that an error has
occurred. Active High indicates Receive code group is
invalid. If CRS_DV is low, RX_ERR has no effect. This is
synchronous with RX_CLK. In DCE mode, this signal must
be grounded.
Receive Error (RMII): Signal is synchronous to
REF_CLK.
Collision Detect (MII): Asserted by the MAC PHY to
indicate that a collision is occurring. In DCE Mode this
signal should be connected to ground. This signal is only
valid in half duplex mode, and is ignored in full duplex
mode
Management Data Clock (MII): Clocks management data
between the PHY and DS33Z11. The clock is derived from
SYSCLKI, with a maximum frequency is 1.67 MHz. The
user must leave this pin unconnected in the DCE Mode.
MII Management Data IO (MII): Data path for control
information between the PHY and DS33Z11. When not
used, pull to logic high externally through a 10kΩ resistor.
The MDC and MDIO pins are used to write or read up to
32 Control and Status Registers in 32 PHY Controllers.
This port can also be used to initiate Auto-Negotiation for
the PHY. The user must leave this pin unconnected in the
DCE Mode.
Address Bit 0: Address bit 0 of the microprocessor
interface. Least Significant Bit
BREO (Hardware Mode): Used in Hardware Mode to
reverse the ordering of HDLC transmit and receive
functions. Active high input. When 0, the first bit received
is the MSB. When 1, bit the first bit received is the LSB.
The software registers used for control of this function are
LI.RPPCL and LI.TPPCL.
Address Bit 1: Address bit 1 of the microprocessor
interface.
SCD (Hardware Mode): Used in Hardware Mode to
disable X
receive paths. Applies to HDLC and X.86 transport. When
1, X
scrambling is enabled. The software registers used for
control of this function are LI.RPPCL and LI.TPPCL.
43
+1 scrambling is disabled. When 0, X
43
+1 bit scrambling for both the transmit and
FUNCTION
43
+1