DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 55

no-image

DS33Z11

Manufacturer Part Number
DS33Z11
Description
Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33Z11

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS33Z11
Manufacturer:
DALLAS
Quantity:
15
Part Number:
DS33Z11
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS33Z11
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS33Z11+
Manufacturer:
Maxim
Quantity:
20
Part Number:
DS33Z11+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS33Z11+UNUSED
Manufacturer:
Maxim Integrated
Quantity:
10 000
DS33Z11 Ethernet Mapper
FCS error monitoring checks the FCS and aborts errored packets. If an FCS error is detected, the FCS errored
packet count is incremented and the packet is marked with an aborted indication. If an FCS error is not detected,
the receive packet count is incremented. The FCS type (16-bit or 32-bit) is programmable. If FCS processing or
packet processing is disabled, FCS error monitoring is not performed.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7]
(or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or
31:24). If bit reordering is enabled, the incoming 8-bit data stream DT[1:8] is output to the Receive FIFO with the
MSB in RFD[0] and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. DT[1] is the first bit received from the
incoming data stream. Bit reordering can be controlled by pin A0 in Hardware Mode.
Once all of the packet processing has been completed, The 8-bit parallel data stream is demultiplexed into a 32-
bit parallel data stream. The Receive FIFO data is passed on to the Receive FIFO with packet start, packet end,
packet abort, and modulus indications. At a packet end, the 32-bit word may contain 1, 2, 3, or 4 bytes of data
depending on the number of bytes in the packet. The modulus indications indicate the number of bytes in the last
data word of the packet.
55 of 172

Related parts for DS33Z11