TMC2242AR2C1 Fairchild Semiconductor, TMC2242AR2C1 Datasheet - Page 3

• Manufacturer Part Number: TMC2242AR2C1
• Description: Video ICs Interp/Decim Filter Digital HB 12B/16B
• Manufacturer: Fairchild Semiconductor
• Type: Digital Half Band Filtersr

Specifications of TMC2242AR2C1

• Operating Supply Voltage: - 0.5 V to + 7 V
• Supply Current: 195 mA
• Maximum Operating Temperature: 70 C
• Package / Case: PLCC-44
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TMC2242A/TMC2242B
Pin Descriptions
Pin Name
Timing Controls
INT
DEC
SYNC
CLK
Data Inputs
SI
Data Outputs
SO
Output Controls
OE
TCO
RND
Power
V
GND
DD
11-0
15-0
2-0
44
1
43
42
40,
37-30,
27-25
4-11,
14-21
3
2
22-24
13,29,
38
12,28,
39,41
PLCC
Pin Number
38
39
37
36
34,
31-24,
21-19
42-44,
1-5,
8-15
41
40
16-18
7, 23,
32
6, 22,
33, 35
MQFP
Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at
1/2 the CLK rate and zeros are inserted in the data stream between valid input
values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and
output results at the full CLK rate.
Decimate. When DEC is LOW and INT is HIGH, the input data register runs at
the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and
output results at 1/2 the CLK rate.
When INT = DEC, the TMC2242A is in equal rate mode. When both INT and DEC
are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and
DEC are LOW, the TMC2242B interpolates with unity gain.
In equal-rate mode, the input and output sample rates equal the chip clock rate.
Synchronization. Incoming data are synchronized by holding SYNC HIGH on
CLK N–1 and LOW on CLK N when the first input data word is present on SI
If DEC = INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW
until resynchronization is desired, or it may be toggled at 1/2 the CLK rate.
Clock. The TMC2242A and TMC2242B operate from a single master clock. All
internal registers, except the output register in decimation mode, are strobed on
the rising edge of CLK. All timing parameters are referenced to the rising edge of
CLK.
Input Data Port. A 12-bit 2's-complement input word is registered by the rising
edge of CLK. In Interpolate Mode, SI
(synchronized by SYNC). SI
Output Data Port. A 16-bit 2's-complement output result is available after the
rising edge of CLK. In Decimate Mode, SO
(synchronized by SYNC). SO
SO
The limiter circuitry ensures that for internal overflow, a valid full-scale output
(7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with
-6dB gain, limits are 3FFF and C000 (TCO=1).
Output Enable. When LOW, SO
high-impedance state. OE is asynchronous with respect to CLK.
Output Format. When TCO is HIGH, output data are in signed 2's-complement
format. When LOW, the output is inverted offset binary.
Rounding Select. These inputs set the position of the effective LSB of the output
result. Outputs below the rounding bit are zeroed (Table 4).
Supply Voltage. +5 Volt power inputs. These should come from the same power
source and be decoupled to GND.
Ground. Ground inputs should be connected to the system digital ground plane.
15
is the MSB.
Pin Function Description
11
15-0
is the MSB.
15-0
is rounded according to the state of RND
11-0
are enabled. When HIGH, SO
is registered on every other CLK
15-0
is registered on every other CLK
PRODUCT SPECIFICATION
15-0
are in a
2-0
11-0
.
.
3