82V2081PPG8 IDT, Integrated Device Technology Inc, 82V2081PPG8 Datasheet - Page 33

• Manufacturer Part Number: 82V2081PPG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2081PPG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.13 INTERRUPT HANDLING
When the INT_PIN[0] bit (GCF, 02H) is ‘0’, the
low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 02H) are ‘01’, the
INT_PIN[1:0] bits are ‘10’, the
Status Register (INTS0, 19H) or (INTS1, 1AH). Every kind of interrupt can
be enabled/disabled individually by the corresponding bit in the register
(INTM0, 14H) or (INTM1, 15H). Some event is reflected by the correspond-
ing bit in the Status Register (STAT0, 17H) or (STAT1, 18H), and the Inter-
rupt Trigger Edge Selection Register can be used to determine how the
Status Register sets the Interrupt Status Register.
the
Table-22 Interrupt Event
3.14 5V TOLERANT I/O PINS
TTL logic.
3.15 RESET OPERATION
•
Arbitrary Waveform Generator
Inband Loopback Deactivate Code Status
All kinds of interrupt of the IDT82V2081 are indicated by the
An active level on the
The interrupt event is captured by the corresponding bit in the Interrupt
After the Interrupt Status Register (INTS0, 19H) or (INTS1, 1AH) is read,
All digital input pins will tolerate 5.0
The chip can be reset in two ways:
INT
Synchronization Status of PRBS/QRSS
Inband Loopback Activate Code Status
Software Reset: Writing to the RST register (01H) will reset the chip
in 1 us.
pin become inactive.
One-Second Timer Expired
Excessive Zeros Received
Code Violation Received
Error Counter Overflow
Driver Failure Detected
Equalizer Out of Range
JA FIFO Underflow
PRBS/QRSS Error
JA FIFO Overflow
Interrupt Event
LOS Detected
AIS Detected
TCLK Loss
INT
pin represents an interrupt of the IDT82V2081.
INT
INT
pin is push-pull active low; when the
pin is push-pull active high.
Overflow
±
10% volts and are compatible with
INT
pin is open drain active
(STAT0, STAT1)
TCLK_LOS
Status bit
IBLBA_S
IBLBD_S
PRBS_S
LOS_S
AIS_S
EQ_S
DF_S
INT
pin.
33
Interrupt Status bit
(INTS0, INTS1)
TCLK_LOS_IS
source:
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
•
flip-flops are reset, and all the registers are initialized to default values.
3.16 POWER SUPPLY
DAC_OV_IS
CNT_OV_IS
IBLBD_IS
TMOV_IS
PRBS_IS
IBLBA_IS
JAOV_IS
JAUD_IS
ERR_IS
LOS_IS
EXZ_IS
AIS_IS
CV_IS
EQ_IS
There are totally fourteen kinds of events that could be the interrupt
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13).Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-22
DF_IS
After reset, all drivers output are in high impedance state, all the internal
This chip uses a single 3.3 V power supply.
Hardware Reset: Asserting the RST pin low for a minimum of 100
ns will reset the chip.
is a summary of all kinds of interrupt and the associated Status
Interrupt Edge Selection bit
IBLBD_IES
PRBS_IES
IBLBA_IES
TCLK_IES
LOS_IES
AIS_IES
(INTES)
EQ_IES
DF_IES
TEMPERATURE RANGES
Interrupt Mask bit
(INTM0, INTM1)
DAC_OV_IM
TIMER_IM
IBLBA_IM
IBLBD_IM
PRBS_IM
JAOV_IM
JAUD_IM
TCLK_IM
ERR_IM
LOS_IM
EXZ_IM
CNT_IM
AIS_IM
EQ_IM
DF_IM
CV_IM
INDUSTRIAL