82V2081PPG8 IDT, Integrated Device Technology Inc, 82V2081PPG8 Datasheet - Page 46

• Manufacturer Part Number: 82V2081PPG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2081PPG8

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.6
Table-47 STAT0: Line Status Register 0 (real time status monitor)
TCLK_LOS
IBLBD_S
IBLBA_S
PRBS_S
Symbol
EQ_S
DF_S
LINE STATUS REGISTERS
(R, Address = 17H)
Bit
5
4
7
6
3
2
Default
0
0
0
0
0
0
In-band Loopback deactivate code receive status indication
Synchronous status indication of PRBS/QRSS (real time)
Equalizer status indication
= 0: In range
= 1: Out of range
In-band Loopback activate code receive status indication
= 0: No Inband Loopback activate code is detected
= 1: Activate signal is detected and then received over a period of more than t ms, with a bit error rate less than 10
2
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit activates the
remote loopback operation in local end.
Note2:
If IBLBA_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an activate code detected interrupt if IBLBA _IES bit is ‘0’;
Any changes of this bit causes an activate code detected interrupt if IBLBA _IES bit is set to ‘1’.
= 0: No Inband Loopback deactivate signal is detected
= 1: The Inband Loopback deactivate signal is detected and then received over a period of more than t, with a bit
error rate less than 10
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit disables the
remote loopback operation.
Note2:
If IBLBD_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a deactivate code detected interrupt if IBLBD _IES bit is ‘0’
Any changes of this bit causes a deactivate code detected interrupt if IBLBD _IES bit is set to ‘1’
= 0: 2
= 1: 2
Note:
If PRBS_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if PRBS_IES bit is set to ‘1’.
TCLK loss indication
= 0: Normal
= 1: TCLK pin has not toggled for more than 70 MCLK cycles.
Note:
If TCLK_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an interrupt if TCLK _IES bit is ‘0’.
Any changes of this bit causes an interrupt if TCLK_IES bit is set to ‘1’.
Line driver status indication
= 0: Normal operation
= 1: Line driver short circuit is detected.
Note:
If DF_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if DF _IES bit is ‘0’.
Any changes of this bit causes an interrupt if DF_IES bit is set to ‘1’.
. The bit remains set as long as the bit error rate does not exceed 10
15
15
-1 (E1) PRBS or 2
-1 (E1) PRBS or 2
-2
. The bit remains set as long as the bit error rate does not exceed 10
20
20
-1 (T1/J1) QRSS is not detected
-1 (T1/J1) QRSS is detected
46
Description
-2
.
TEMPERATURE RANGES
-2
.
INDUSTRIAL
-