WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 120

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 11
4.3.8
Note:
4.3.9
Cortina Systems
Port Address Scheme
MII Sectionalization
When sectionalized into two quad sections, the MDIO bus splits into two separate PHY
access ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII
isolate function is unaffected and operates normally. Sectionalization is selected by pulling
pin 176 (Section) High on the initial power-up sequence (refer to
applications that need sectionalization, such as 1x8 and 2x4 and have a single MDIO bus
structure, it is necessary that the addressing scheme be contiguous. For example, the first
eight ports are addressed 0-7, so the next four ports must be addressed 8-11.
The BGA15 package does not support the MII sectionalization feature.
MII Interrupts
The LXT9785/LXT9785E provides a single per-section interrupt pin that is available to all
ports. Interrupt logic is shown in
dedicated interrupt registers for each port. Register 18 provides interrupt enable and mask
functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1 enables a
port to request interrupt via the MDINT_L pin. An active Low on this pin indicates a status
change on the device. Because it is a shared interrupt, there is no indication which port is
requesting interrupt service (see
There are five conditions that may cause an interrupt:
®
• Auto-negotiation complete.
• Speed status change.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785
LXT9785/9785E
Port 0
Port 1
Port 2
Port 6
Port 3
Port 4
Port 5
Port 7
Figure
Figure
BASE ADD_<4:0>
(example ADD_<4:0> = 4)
PHY ADD_<4:0> (BASE+0)
ex. 4
PHY ADD_<4:0> (BASE+1)
ex. 5
PHY ADD_<4:0> (BASE+2)
ex. 6
PHY ADD_<4:0> (BASE+3)
ex. 7
PHY ADD_<4:0> (BASE+4)
ex. 8
PHY ADD_<4:0> (BASE+5)
ex. 9
PHY ADD_<4:0> (BASE+7)
ex. 11
PHY ADD_<4:0> (BASE+6)
ex. 10
12. The LXT9785/LXT9785E also provides two
12).
Figure
Interface (MII) Interfaces
4.3 Media Independent
13). In
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