WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 192

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 83
Table 84
Cortina Systems
Register Set
Control Register (Address 0)
®
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
6. Link Status is reported in 10 Mbps mode as down and in 100 Mbps mode as up in loopback mode.
Address
14
30 - 31
Bit
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
15
13
12
11
10
9
8
28
29
6
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
the pin(s) are latched at startup or hardware reset.
Global Hardware Configuration Settings , on page
Register bits 17.12 (Receive Status) and 17.13 (Transmit Status) are not updated in 10 Mbps loopback
mode.
Name
RESET_L
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Isolate
Restart
Auto-Negotiation
Duplex Mode
Reserved
Cable Diagnostics Register (Address 29, Hex 1D)
Reserved
Register Name
Description
0 = Normal operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
Not recommended to enable auto-negotiation
while in internal loopback operation.
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
0 = Normal operation
1 = Power-down
0 = Normal operation
1 = Electrically isolate PHY from RMII/SMII/SS-
0 = Normal operation
1 = Restart auto-negotiation process
0 = Half-duplex
1 = Full-duplex
0.6
1
1
0
0
SMII interfaces
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
126.
Bit Assignments
N/A
Refer to
N/A
7.0 Register Definitions
Table 101 on page 209
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SC
SC
1
LSHR
LSHR
LSHR
LSHR
Default
Table 42,
Page 192
0
0
0
0
2
3,4
3,4
3,5
3,4