WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 44

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 13
Cortina Systems
Miscellaneous Signal Descriptions – PQFP (Sheet 2 of 4)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
3. The LINKHOLD ability is available only for stepping 4 (Revision D0).
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
PQFP
174
175
178
177
176
50
88
89
90
91
92
Designation
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Pin/Ball
PBGA
M15
L17,
L14
M2,
M3,
N1,
L16
L15
L4,
D5
N2
MODESEL_1
MODESEL_0
PWRDWN
RESET_L
SECTION
Symbol
PAUSE
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
I, ID, ST
I, ST, ID
I, ST, ID
I, ST, ID
I, ST, ID
I, ST, IP
Type
1
Signal Description
Pause Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 4.10 for
all ports. This register bit can be read and overwritten
after startup / reset.
When High, the LXT9785/LXT9785E advertises Pause
capabilities on all ports during auto-negotiation.
This pin is shared with RMII-RxER1. An external pull-
up resistor (see applications section for value) can be
used to set Pause active while RxER1 is three-stated
during H/W reset. If no pull-up is used, the default
Pause state is set inactive via the internal pull-down
resistor.
Power-Down.
When High, forces the LXT9785/LXT9785E into global
power-down mode.
Pin is not on JTAG chain.
Reset.
This active low input is ORed with the control register
Reset Register bit 0.15. When held Low, all outputs are
forced to inactive state.
Pin is not on JTAG chain.
Address <4:0>.
Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY
address.
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
Mode Select[1:0].
00 = RMII
01 = SMII
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all RMII, SMII, or SS-SMII.
Sectionalization Select.
This pin selects sectionalization into separate ports.
0 = 1x8 ports,
1 = 2x4 ports
2
3.2 PQFP Signal Descriptions
Page 44