WBLXT9785HE.D0-865114 Cortina Systems Inc, WBLXT9785HE.D0-865114 Datasheet - Page 178

• Manufacturer Part Number: WBLXT9785HE.D0-865114
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HE.D0-865114

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 65
Figure 44
Table 66
Cortina Systems
SMII - 10BASE-T Receive Timing Parameters (Sheet 2 of 2)
SMII - 10BASE-T Transmit Timing
SMII-10BASE-T Transmit Timing Parameters
®
Receive Start-of-Idle to CRS
de-asserted
SYNC setup to REFCLK rising
edge
SYNC hold from REFCLK rising
edge
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
SYNC hold to REFCLK rising edge and
TxData hold from REFCLK rising edge
TxEN sampled to start-of-frame
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
testing.
100BASE-TX or 100BASE-FX).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
REFCLK
Parameter
TxData
SYNC
TPFO
Parameter
t4
t5
t6
Sym
t
1
t
2
–
1.5
1.0
Min
t
3
Sym
t1
t2
t3
17
–
–
Typ1
Min
1.5
1.0
–
18
–
–
Max
Typ1
t
BT
ns
ns
1
10
Units
–
–
3
t
2
Max
Synchronous sampling of SMII
14
–
–
Test Conditions
Units
6.0 Test Specifications
BT
ns
ns
2
–
–
Conditions
Test
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–
–
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