PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet
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PIC18F64J11T-I/PT Summary of contents
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... High-Performance Microcontrollers 2010 Microchip Technology Inc. PIC18F85J11 Family Data Sheet with nanoWatt Technology 64/80-Pin, DS39774D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F84J11 16K 8192 PIC18F85J11 32K 16384 2010 Microchip Technology Inc. PIC18F85J11 FAMILY External Memory Bus (PIC18F8XJ11 only): • Address Capability Mbytes • 8-Bit or 16-Bit Interface • 12-Bit, 16-Bit and 20-Bit Addressing modes Flexible Oscillator Structure: • Two Crystal modes, 4-25 MHz • ...
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... RF2/AN7/C1OUT Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting. DS39774D-page 4 Pins are up to 5.5V tolerant PIC18F63J11 PIC18F64J11 PIC18F65J11 RB0/INT0 47 RB1/INT1 46 RB2/INT2 45 RB3/INT3 44 RB4/KBI0 43 RB5/KBI1 42 RB6/KBI2/PGC RA6/OSC2/CLKO 39 RA7/OSC1/CLKI RB7/KBI3/PGD 37 36 RC5/SDO RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 33 2010 Microchip Technology Inc. ...
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... DDCORE CAP RF7/AN5/SS 13 RF6/AN11 14 RF5/AN10/CV 15 REF RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 Note 1: The CCP2 pin placement depends on the settings of the CCP2MX and EMB<1:0> Configuration bits. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY PIC18F83J11 51 PIC18F84J11 PIC18F85J11 Pins are up to 5.5V tolerant RJ2/WRL ...
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... Packaging Information.............................................................................................................................................................. 387 Appendix A: Revision History............................................................................................................................................................. 393 Appendix B: Migration Between High-End Device Families............................................................................................................... 393 Index .................................................................................................................................................................................................. 395 The Microchip Web Site ..................................................................................................................................................................... 405 Customer Change Notification Service .............................................................................................................................................. 405 Customer Support .............................................................................................................................................................................. 405 Reader Response .............................................................................................................................................................................. 406 Product Identification System............................................................................................................................................................. 407 DS39774D-page 6 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY DS39774D-page 7 ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 8 2010 Microchip Technology Inc. ...
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... MHz, for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • ...
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... All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. 2 C™ devices, 2048 bytes for 2010 Microchip Technology Inc. ...
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... Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications (PSP) External Memory Bus 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F85J11 FAMILY PIC18F63J11 PIC18F64J11 DC – 40 MHz 8K 16K 4096 8192 1024 1024 27 ...
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... Oscillator 8 8 Reset ALU<8> Timer BOR and (3) LVD MCLR SS ADC Timer2 Timer3 10-Bit MSSP AUSART EUSART PORTA (1,2) RA0:RA7 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PRODL PORTE (1) RE0:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG4 Comparators 2010 Microchip Technology Inc. ...
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... RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more information 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Data Latch 8 ...
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... Digital I/O. Open-drain when configured as output Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog Input 4. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... I/O ST EUSART synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C™ mode 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... Chip select control for Parallel Slave Port. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... External memory address/data 6. I/O TTL Parallel Slave Port data. I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Slave Port data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog Input 11. I/O ST Digital I/O. O Analog Analog Input 5. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port ...
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... External memory address/data 18. I/O ST Digital I/O. I/O TTL External memory address/data 19. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Digital I/O. I/O ST Digital I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 30 2010 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... MHz Source (INTOSC) INTRC Source 31 kHz (INTRC) 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Five of these are selected by the user by programming the FOSC<2:0> Configuration bits. The sixth mode (INTRC) may be invoked under software control; it can also be configured as the default mode on device Resets ...
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... Phase Locked Loop (PLL) in Internal Oscillator modes (see Section 3.4.3 “PLL Frequency Multiplier”). (1) R/W-0 R (2) (2) IRCF0 OSTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (3) (1) (4) R-0 R/W-0 R/W-0 (4) (4) IOFS SCS1 SCS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Section 3.4 “External Oscillator Modes”. The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 R/W-0 R/W-0 ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. block is selected whenever 2010 Microchip Technology Inc. ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 3-2 for additional information. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq ...
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... PLL, regardless of the chosen oscillator configuration. It also allows additional flexibility for controlling the application’s clock speed in software. FIGURE 3-5: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 Phase Comparator OSC1 Mode F OUT Loop Filter 4 VCO 2010 Microchip Technology Inc. SYSCLK ...
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... The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC or vice versa. The frequency of INTRC is not affected by OSCTUNE. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 3.5.3 INTOSC FREQUENCY DRIFT The INTOSC frequency may drift as V ture changes, and can affect the controller operation in a variety of ways ...
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... There is a delay of interval T Table 26-12), following POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level I/O pin, RA7, direction controlled by TRISA<7> (parameter 38, CSD OSC2 Pin 2010 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<2:0> ...
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... SEC_RUN mode is entered by setting the SCS<1:0> bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F85J11 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2) ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD 2010 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 50 2010 Microchip Technology Inc. ...
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... INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39774D-page 52 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises to the point where DD regulator output is sufficient, the Power-up Timer will execute the additional time delay. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY FIGURE 5- ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 5-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT 2010 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F85J11 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 ...
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... DS39774D-page 56 Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY MCLR Resets WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY MCLR Resets WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu u-uu uuuu uuuu uuuu uuuu ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY MCLR Resets WDT Reset ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 62 2010 Microchip Technology Inc. ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Section 23.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F85J11 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F63J11 8 1FF8h to 1FFFh PIC18F83J11 PIC18F64J11 16 3FF8h to 3FFFh PIC18F84J11 PIC18F65J11 32 7FF8h to 7FFFh PIC18F85J11 2010 Microchip Technology Inc. through Word Addresses ...
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... Unimplemented: Read as ‘0’ Note 1: CONFIG3L and its associated bits are implemented only in 80-pin devices. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory ...
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... Yes Yes Yes (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes 2010 Microchip Technology Inc. ...
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... TOSH TOSL 00h 1Ah 34h 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2010 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. 2010 Microchip Technology Inc. ...
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... Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh 2010 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Data Memory 000h ...
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... LATC F6Bh — LATB F6Ah CCPR1H LATA F69h CCPR1L (3) PORTJ F68h CCP1CON (3) PORTH F67h CCPR2H PORTG F66h CCPR2L PORTF F65h CCP2CON PORTE F64h SPBRG2 PORTD F63h RCREG2 PORTC F62h TXREG2 PORTB F61h TXSTA2 PORTA F60h RCSTA2 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY ...
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... TRMT TX9D 59, 224 0000 0010 OERR RX9D 59, 225 0000 000x 59, 90 ---- ---- WR — 59, 91 ---0 x00- C™ Slave mode. See Section 17.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY ...
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... CCP2M1 CCP2M0 61, 169 --00 0000 61, 248 0000 0000 61, 253 0000 0000 61, 251 0000 0000 TRMT TX9D 61, 246 0000 -010 OERR RX9D 61, 247 0000 000x C™ Slave mode. See Section 17.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue 2010 Microchip Technology Inc. Stack Pointer ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. 2010 Microchip Technology Inc. ...
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... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 6.6.2 INSTRUCTIONS AFFECTED BY ...
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... FSR2H F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h Bank 1 001001da through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory 2010 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 88 2010 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Figure 7-3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 2010 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT ...
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... The CPU will stall for the duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2010 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 96
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block 2010 Microchip Technology Inc. ...
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... EECON2 EEPROM Control Register 2 (not a physical register) EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 7.6 Flash Program Operation During Code Protection See Section 23.6 “Program Verification and Code Protection” ...
Page 98
... PIC18F85J11 FAMILY NOTES: DS39774D-page 98 2010 Microchip Technology Inc. ...
Page 99
... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 100
... Data Width Modes”. These bits have no effect when an 8-Bit Data Width mode is selected. R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WM1 WM0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F85J11 FAMILY 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-Bit Data Width modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. 2010 Microchip Technology Inc. register ...
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... The upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD< ...
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... The obvious limitation to this method is that the table write must be done in pairs on a specific word even address boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines 2010 Microchip Technology Inc. ...
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... The upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 106
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive 2010 Microchip Technology Inc. ...
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... This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 108
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 55h 0Eh ABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive 2010 Microchip Technology Inc. ...
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... If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
Page 110
... PIC18F85J11 FAMILY NOTES: DS39774D-page 110 2010 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F85J11 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H 2010 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 114
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 116
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39774D-page 116 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 ...
Page 118
... R-0 R/W-0 U-0 TX1IF SSPIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
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... The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J11 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘ ...
Page 120
... No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 Unimplemented: Read as ‘0’ DS39774D-page 120 R-0 U-0 R/W-0 TX2IF — CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 CCP1IF — bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ DS39774D-page 122 U-0 R/W-0 R/W-0 — BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R/W-0 U-0 TMR3IE — bit Bit is unknown ...
Page 123
... CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP1IE: CCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R-0 U-0 R/W-0 TX2IE — CCP2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 124
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39774D-page 124 R/W-1 R/W-1 U-0 TX1IP SSPIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2010 Microchip Technology Inc. ...
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... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J11 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 126
... CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ DS39774D-page 126 R-1 U-0 R/W-1 TX2IP — CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 U-0 CCP1IP — bit Bit is unknown 2010 Microchip Technology Inc. ...
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... For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS 2010 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 11 ...
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... OUTPUT (USARTs SHOWN AS EXAMPLES +5V 3. (at logic ‘1’) and RA7/OSC1/CLKI normally INITIALIZING PORTA ; Initialize PORTA by ; clearing output latches ; Alternate method to ; clear output data latches ; Configure A/D ; Value used to initialize ; data direction ; Set RA<7, 5:0> as inputs, ; RA<6> as output 2010 Microchip Technology Inc. ...
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... Legend: — = Unimplemented, read as ‘0’ Don’t care. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O I/O ...
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... EXAMPLE 11-2: INITIALIZING PORTB CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches CLRF LATB ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs 2010 Microchip Technology Inc. delay. CY ...
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... TRISB6 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O I/O Type O DIG LATB<0> data output. I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. ...
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... EXAMPLE 11-3: INITIALIZING PORTC CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 2010 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O Description ...
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... Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 — LATG4 LATG3 LATG2 TRISG4 TRISG3 TRISG2 Reset Bit 1 Bit 0 Values on page RC1 RC0 60 LATC1 LATC0 60 TRISC1 TRISC0 60 LATG1 LATG0 60 TRISG1 TRISG0 60 2010 Microchip Technology Inc. ...
Page 137
... When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY PORTD can also be configured to function as an 8-bit wide, parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface) ...
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... External memory interface, address/data bit 6 output. I TTL External memory interface, data bit 6 input. O DIG PSP read output data (LATD<6>); takes priority over port data. I TTL PSP write data input. Description (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 2010 Microchip Technology Inc. ...
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... LATD LATD7 LATD6 TRISD TRISD7 TRISD6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O I/O Type O DIG LATD<7> data output PORTD<7> data input. O DIG External memory interface, address/data bit 7 output ...
Page 140
... CCP2MX Configuration bit. EXAMPLE 11-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs 2010 Microchip Technology Inc. ...
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... Note 1: Available on 80-pin devices only. 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O I/O Type O DIG LATE< ...
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... Bit 3 Bit 2 RE5 RE4 RE3 RE2 LATE5 LATE4 LATE3 LATE2 TRISE5 TRISE4 TRISE3 TRISE2 (1) RJPU RG4 RG3 RG2 TRISG4 TRISG3 TRISG2 Reset Bit 1 Bit 0 Values on page RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 RG1 RG0 60 TRISG1 TRISG0 60 2010 Microchip Technology Inc. ...
Page 143
... Note 1: On device Resets, pins, RF<6:1>, are configured as analog inputs and are read as ‘0’ configure PORTF as digital I/O, turn off comparators and set ADCON1 value. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY EXAMPLE 11-6: INITIALIZING PORTF CLRF PORTF ...
Page 144
... LATF4 LATF3 LATF2 TRISF4 TRISF3 TRISF2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 Description Reset Bit 1 Bit 0 Values on page RF1 — 60 LATF1 — 60 TRISF1 — 60 PCFG1 PCFG0 59 CM1 CM0 59 CVR1 CVR0 59 2010 Microchip Technology Inc. ...
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... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
Page 146
... PORTG<3> data input. DIG LATG<4> data output PORTG<4> data input. Bit 5 Bit 4 Bit 3 Bit 2 (1) RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 TRISG4 TRISG3 TRISG2 Description Reset Bit 1 Bit 0 Values on page RG1 RG0 60 LATG1 LATG0 60 TRISG1 TRISG0 60 2010 Microchip Technology Inc. ...
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... TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 PORTH RH7 RH6 LATH LATH7 LATH6 TRISH TRISH7 TRISH6 2010 Microchip Technology Inc. PIC18F85J11 FAMILY EXAMPLE 11-8: CLRF PORTH CLRF LATH MOVLW 0Fh MOVWF ADCON1 MOVLW 0CFh MOVWF ...
Page 148
... The TRISJ bits are also overridden. EXAMPLE 11-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTJ by ; clearing output latches CLRF LATJ ; Alternate method ; to clear output latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2010 Microchip Technology Inc. ...
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... PORTJ RJ7 RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTJ. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
Page 150
... Q WR LATD CK or PORTD Data Latch TTL PORTD EN EN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes 2010 Microchip Technology Inc. RDx pin RD TTL TTL CS TTL WR and ...
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... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-4: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 ...
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... TX1IE SSP1IE RC1IP TX1IP SSP1IP Reset Bit 1 Bit 0 Values on page RD1 RD0 60 LATD1 LATD0 60 TRISD1 TRISD0 60 RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 — — — 59 INT0IF RBIF 57 — TMR2IF TMR1IF 59 — TMR2IE TMR1IE 59 — TMR2IP TMR1IP 59 2010 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... Sync with Internal Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0L TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 155
... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 12.3.1 ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 156 2010 Microchip Technology Inc. ...
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... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F85J11 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
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... TIMER1 LP OSCILLATOR C1 PIC18F85J11 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER1 (2,3,4) OSCILLATOR Oscillator Freq. C1 Type ( ...
Page 160
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 2010 Microchip Technology Inc. ...
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... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 162
... PIC18F85J11 FAMILY NOTES: DS39774D-page 162 2010 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF TX1IE SSPIE TX1IP SSPIP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 — TMR2IF TMR1IF 59 — TMR2IE TMR1IE 59 — TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
Page 165
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F85J11 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...
Page 166
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 167
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 168
... PIC18F85J11 FAMILY NOTES: DS39774D-page 168 2010 Microchip Technology Inc. ...
Page 169
... PWM mode Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
Page 170
... TMR1 TMR3 CCP1 CCP2 TMR2 Timer3 is used for all Capture and Compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. 2010 Microchip Technology Inc. ...
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... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). 2010 Microchip Technology Inc. PIC18F85J11 FAMILY Interaction DS39774D-page 171 ...
Page 172
... CAPTURE PRESCALERS ; Turn CCP module off ; new prescaler mode ; value and CCP ON ; Load CCP2CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L 2010 Microchip Technology Inc. ...
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... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 16.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP2 interrupt is generated, if enabled, and the CCP2IE bit is set. ...
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... CCP2M2 CCP2M1 CCP2M0 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 PD POR BOR 58 CCP1IF — 59 CCP1IE — 59 CCP1IP — 59 TMR3IF — 59 TMR3IE — 59 TMR3IP — 59 TRISC1 TRISC0 60 — TRISE1 TRISE0 60 TRISG1 TRISG0 TMR1CS TMR1ON TMR3CS TMR3ON 2010 Microchip Technology Inc. ...
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... The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY A PWM output (Figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... PWM period, the CCP2 pin will not be cleared. 9.77 kHz 39.06 kHz FFh FFh OSC log --------------- F PWM = -----------------------------bits 2 log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 2010 Microchip Technology Inc. ...
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... CCPR2H Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
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... PIC18F85J11 FAMILY NOTES: DS39774D-page 178 2010 Microchip Technology Inc. ...
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... MSSP module 2 is operated in SPI mode. Additional details are provided under the individual sections. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPBUF and the SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) the SSPBUF is not R0 R bit Bit is unknown 2010 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, this pin must be properly configured as an input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I 2010 Microchip Technology Inc. PIC18F85J11 FAMILY R/W-0 R/W-0 (2) (3) ...
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... SSPBUF register. Additionally, the SSPSTAT register indicates the various status conditions. Note: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between transmission. 2010 Microchip Technology Inc. each ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F85J11 FAMILY to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the SPIOD bit (TRISG< ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
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... Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC18F85J11 FAMILY driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes pull-up/pull-down resistors may be desirable depending on the application. ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39774D-page 186 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 3 bit 2 bit 5 bit 4 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
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... SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in SPI mode. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY mode and Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set, and if enabled, will wake the device ...
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... SSPIF interrupt is set. Addr Match During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the the SSPBUF is not 2010 Microchip Technology Inc. ...
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... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 2 C™ MODE) ...
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... DS39774D-page 190 2 C™ MODE) R/W-0 R/W-0 (1) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /(4 * (SSPADD + 1)) OSC R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a 2010 Microchip Technology Inc. ...
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... Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 2 C™ MASTER MODE) R/W-0 R/W-0 ...
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... C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS39774D-page 192 2 C™ SLAVE MODE) R/W-0 R/W-0 ADMSK4 ADMSK3 ADMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 (1) ADMSK1 SEN bit Bit is unknown 2010 Microchip Technology Inc. ...
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... SSPBUF, but the SSPIF bit is set. The BF bit is cleared by reading the SSPBUF register, while the SSPOV bit is cleared through software. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY The SCL clock input must have a minimum high and low for proper operation. The high and low times of the ...
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... They 2 C slave can only affect the lower address bits. Note 1: ADMSK1 masks the two Least Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking. 2010 Microchip Technology Inc. ...
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... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more details. 2010 Microchip Technology Inc. PIC18F85J11 FAMILY 17.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F85J11 FAMILY 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) DS39774D-page 196 2010 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESSING) 2010 Microchip Technology Inc. PIC18F85J11 FAMILY DS39774D-page 197 ...
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... PIC18F85J11 FAMILY 2 FIGURE 17-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) DS39774D-page 198 2010 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) 2010 Microchip Technology Inc. PIC18F85J11 FAMILY DS39774D-page 199 ...
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... PIC18F85J11 FAMILY 2 FIGURE 17-12: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESSING) DS39774D-page 200 2010 Microchip Technology Inc. ...