PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 173

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

16.3
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
The action on the pin is based on the value of the mode
select bits (CCP2M<3:0>). At the same time, the
interrupt flag bit, CCP2IF, is set.
16.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
16.3.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCPx module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 16-3:
 2010 Microchip Technology Inc.
the I/O latch)
Note:
Compare Mode
CCPx PIN CONFIGURATION
Clearing the CCP2CON register will force
the RB3, RC1 or RE7 compare output
latch (depending on device configuration)
to the default low level. This is not the
PORTB, PORTC or PORTE I/O data latch.
TIMER1/TIMER3 MODE SELECTION
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR2H
CCPR1H
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR2L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP1IF
T3CCP2
Set CCP2IF
(Timer1/Timer3 Reset, A/D Trigger)
PIC18F85J11 FAMILY
16.3.3
When the Generate Software Interrupt mode is chosen
(CCP2M<3:0> = 1010), the CCP2 pin is not affected.
Only a CCP2 interrupt is generated, if enabled, and the
CCP2IE bit is set.
16.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP2M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a Programmable
Period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
Special Event Trigger
Special Event Trigger
Note:
CCP1CON<3:0>
(Timer1 Reset)
CCP2CON<3:0>
Output
Compare
Output
Logic
4
Logic
4
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion even when the A/D
Converter is enabled.
Special
S
R
S
R
Q
Q
Output Enable
Output Enable
Event
TRIS
TRIS
DS39774D-page 173
CCP1 Pin
Trigger
CCP2 Pin
mode