PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 256

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
19.4.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 19-8:
TABLE 19-7:
DS39774D-page 256
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2 AUSART Receive Register
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Name
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RX2/DT2 Pin
TX2/CK2 Pin
Initialize the SPBRG2 register for the appropriate
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
(Interrupt)
CREN bit
RC2IF bit
RCREG2
bit SREN
SREN bit
Write to
Read
AUSART SYNCHRONOUS
MASTER RECEPTION
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL
Q2
CSRC
SPEN
Bit 7
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Bit 6
RX9
TX9
—
—
—
bit 0
TMR0IE
RC2IF
RC2IE
RC2IP
SREN
TXEN
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit 5
bit 1
bit 2
INT0IE
CREN
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
bit 3
ADDEN
RBIE
Bit 3
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
—
—
—
—
bit 4
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RC2IF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP2IF
CCP2IE
CCP2IP
BRGH
FERR
Bit 2
bit 5
CCP1IE
CCP1IP
CCP1IF
bit 6
INT0IF
OERR
TRMT
Bit 1
 2010 Microchip Technology Inc.
RX9D
TX9D
RBIF
Bit 0
bit 7
—
—
—
Q1 Q2 Q3 Q4
on page
Values
Reset
‘0’
57
59
59
59
61
61
61
61