PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 133

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

TABLE 11-5:
TABLE 11-6:
 2010 Microchip Technology Inc.
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/
CCP2
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
PORTB
LATB
TRISB
INTCON
INTCON2
INTCON3
Legend: Shaded cells are not used by PORTB.
Name
Pin Name
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin
devices only). Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD is enabled.
GIE/GIEH PEIE/GIEL
TRISB7
LATB7
INT2IP
RBPU
Bit 7
RB7
Function
CCP2
PORTB FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
INT0
INT1
INT2
INT3
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
(1)
INTEDG0 INTEDG1 INTEDG2 INTEDG3
TRISB6
INT1IP
LATB6
Setting
Bit 6
RB6
TRIS
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
1
x
0
1
1
x
x
TMR0IE
I/O
TRISB5
O
O
O
O
O
O
O
O
O
O
INT3IE
LATB5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bit 5
RB5
Type
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
TRISB4
INT0IE
INT2IE
LATB4
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 0 input.
LATB<1> data output.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 1 input.
LATB<2> data output.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 2 input.
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 3 input.
CCP2 compare output and CCP2 PWM output; takes priority over port data.
CCP2 capture input.
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Bit 4
RB4
PIC18F85J11 FAMILY
TRISB3
INT1IE
LATB3
RBIE
Bit 3
RB3
TMR0IF
TMR0IP
TRISB2
INT3IF
LATB2
Bit 2
RB2
Description
TRISB1
INT0IF
INT3IP
INT2IF
LATB1
Bit 1
RB1
TRISB0
INT1IF
LATB0
RBIF
RBIP
Bit 0
RB0
DS39774D-page 133
(2)
(2)
on page
Values
Reset
(2)
60
60
60
57
57
57