PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 281

16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R

PIC18F64J11T-I/PT

Manufacturer Part Number
PIC18F64J11T-I/PT
Description
16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F64J11T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F64J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 23-1:
REGISTER 23-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
bit 2
bit 1-0
Note 1:
R/WO-1
DEBUG
U-0
2:
(1)
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
This bit should always be maintained as ‘0’.
DEBUG: Background Debugger Enable bit
1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins
0 = Background debugger is enabled; RB6 and RB7 are dedicated to in-circuit debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Unimplemented: Read as ‘1’
Unimplemented: Read as ‘0’
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
Unimplemented: Read as ‘0’
R/WO-1
XINST
U-0
(1)
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
WO = Write-Once bit
WO = Write-Once bit
STVREN
R/WO-1
U-0
(1)
(1)
(2)
U-0
U-0
(1)
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
PIC18F85J11 FAMILY
U-0
U-0
(2)
R/WO-1
CP0
U-0
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U-0
U-0
DS39774D-page 281
R/WO-1
WDTEN
U-0
bit 0
bit 0

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