PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 404

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
Timing Diagrams and Specifications
DS39774D-page 404
Parallel Slave Port (PSP) Read ............................... 152
Parallel Slave Port (PSP) Write ............................... 151
Program Memory Read ............................................ 370
PWM Output ............................................................ 175
Repeated Start Condition ......................................... 212
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 238
Slave Synchronization ............................................. 185
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 184
SPI Mode (Slave Mode, CKE = 0) ........................... 186
SPI Mode (Slave Mode, CKE = 1) ........................... 186
Synchronous Reception
Synchronous Transmission .............................. 239, 254
Synchronous Transmission
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 373
Transition for Entry to Idle Mode ................................ 48
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 46
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 368, 370
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Start-up Timer (OST) and Power-up
Timer (PWRT) .................................................. 372
V
(Through TXEN) ....................................... 240, 255
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTRC to HSPLL) ........................................... 290
PRI_RUN Mode ................................................. 46
PRI_RUN Mode (HSPLL) .................................. 45
(CCP1, CCP2) ................................................. 374
Requirements ................................................... 383
(Master Mode, SREN) ............................. 241, 256
Requirements .................................................. 383
DD
Rise > T
PWRT
DD
) ............................................ 55
, V
DD
DD
DD
), Case 1 ....................... 55
), Case 2 ....................... 55
Rise < T
DD
,
PWRT
) ........... 54
Top-of-Stack Access .......................................................... 67
TSTFSZ ........................................................................... 339
Two-Speed Start-up ................................................. 279, 290
Two-Word Instructions
V
V
Voltage Reference Specifications .................................... 363
Voltage Regulator (On-Chip) ........................................... 288
W
Watchdog Timer (WDT) ........................................... 279, 286
WCOL ...................................................... 211, 212, 213, 216
WCOL Status Flag ................................... 211, 212, 213, 216
WWW Address ................................................................ 405
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 339
XORWF ........................................................................... 340
DDCORE
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
External Clock Requirements .................................. 366
I
I
Internal RC Accuracy ............................................... 367
MSSP I
MSSP I
PLL Clock ................................................................ 367
Program Memory Write Requirements .................... 371
Reset, Watchdog Timer, Oscillator Start-up Timer,
Timer0 and Timer1 External Clock
Example Cases .......................................................... 71
Brown-out Reset (BOR) ........................................... 289
Low-Voltage Detection (LVD) .................................. 288
Operation in Sleep Mode ......................................... 289
Power-up Requirements .......................................... 289
Associated Registers ............................................... 287
Control Register ....................................................... 286
Programming Considerations .................................. 286
2
2
C Bus Data Requirements (Slave Mode) .............. 380
C Bus Start/Stop Bits Requirements
/V
(Master Mode, CKE = 0) .................................. 375
(Master Mode, CKE = 1) .................................. 376
(Slave Mode, CKE = 0) .................................... 377
Requirements (CKE = 1) ................................. 378
(Slave Mode) ................................................... 379
Power-up Timer and Brown-out Reset
Requirements .................................................. 372
Requirements .................................................. 373
CAP
2
2
C Bus Data Requirements ......................... 382
C Bus Start/Stop Bits Requirements .......... 381
Pin .......................................................... 288
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