PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 299

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

25.0
The PIC18F85J11 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
25.1
The standard PIC18 instruction set adds many
enhancements to the previous PIC
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-Oriented operations
• Bit-Oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The File Select Register designator, ‘f’, specifies which
File Select Register is to be used by the instruction.
The destination designator, ‘d’, specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the File Select Register specified in
the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the File Select Register
designator, ‘f’, represents the number of the file in
which the bit is located.
 2010 Microchip Technology Inc.
The File Select Register (specified by ‘f’).
The destination of the result (specified by ‘d’).
The accessed memory (specified by ‘a’).
The File Select Register (specified by ‘f’).
The bit in the File Select Register (specified by
‘b’).
The accessed memory (specified by ‘a’).
INSTRUCTION SET SUMMARY
Standard Instruction Set
®
MCU instruction
PIC18F85J11 FAMILY
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a File Select
• The desired FSR register to load the literal value
• No operand required (specified by ‘—’).
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’).
• The mode of the CALL or RETURN instructions
• The mode of the table read and table write
• No operand required (specified by ‘—’).
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 25-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The instruction set summary, shown in Table 25-2, lists
the standard instructions recognized by the Microchip
MPASM
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
Register (specified by ‘k’).
into (specified by ‘f’).
(specified by ‘s’).
instructions (specified by ‘m’).
TM
Assembler.
DS39774D-page 299