PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 235

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

18.3.2
The receiver block diagram is shown in Figure 18-6.
The data is received on the RX1 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
FIGURE 18-6:
 2010 Microchip Technology Inc.
Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, RC1IE.
If 9-bit reception is desired, set bit, RX9.
Enable the reception by setting bit, CREN.
Flag bit, RC1IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC1IE, was set.
Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG1 register.
If any error occurred, clear the error by clearing
enable bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
EUSART ASYNCHRONOUS
RECEIVER
RX1
BRG16
OSC
. This mode would typically be used
EUSART RECEIVE BLOCK DIAGRAM
SPBRGH1
Baud Rate Generator
x64 Baud Rate CLK
and Control
Pin Buffer
SPEN
SPBRG1
Recovery
Interrupt
Data
 64
 16
 4
or
or
CREN
PIC18F85J11 FAMILY
18.3.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
RX9
Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RC1IP
bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RC1IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC1IE and GIE bits are set.
Read the RCSTA1 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREG1 to determine if the device is
being addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
MSb
Stop
RC1IF
RC1IE
RX9D
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
(8)
OERR
7
RSR Register
RCREG1 Register

8
Data Bus
1
FERR
0
DS39774D-page 235
Start
LSb
FIFO