PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
TABLE 6-4:
DS39774D-page 80
SPBRGH1
BAUDCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
Legend:
Note 1:
File Name
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL Frequency
Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
EUSART Baud Rate Generator High Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
AUSART Baud Rate Generator Register
AUSART Receive Register
AUSART Transmit Register
ABDOVF
CSRC
SPEN
Bit 7
—
—
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
RCIDL
Bit 6
RX9
TX9
—
—
RXDTP
DC1B1
DC2B1
SREN
TXEN
Bit 5
TXCKP
DC1B0
DC2B0
SYNC
CREN
Bit 4
CCP1M3
CCP2M3
ADDEN
BRG16
Bit 3
—
CCP1M2
CCP2M2
BRGH
FERR
Bit 2
—
2
C™ Slave mode. See Section 17.4.3.2 “Address
CCP1M1
CCP2M1
TRMT
OERR
WUE
Bit 1
 2010 Microchip Technology Inc.
CCP1M0
CCP2M0
ABDEN
TX9D
RX9D
Bit 0
0000 0000
01-0 0-00
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
POR, BOR
Value on
on page
Details
60, 228
60, 226
60, 170
60, 170
60, 169
61, 170
61, 170
61, 169
61, 248
61, 253
61, 251
61, 246
61, 247