PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 40

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

PIC18F85J11 FAMILY
3.4.2
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 3-4:
DS39774D-page 40
Clock from
Ext. System
Clock from
Ext. System
EXTERNAL CLOCK INPUT
(EC MODES)
F
or RA6
Open
OSC
/4
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1/CLKI
OSC2/CLKO
OSC1
OSC2
PIC18F85J11
PIC18F85J11
(HS Mode)
Configuration bits (CONFIG2L<2:0>) to either ‘110’ (for
disables the PLL, regardless of the chosen oscillator
controlling the application’s clock speed in software.
3.4.3
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscillat-
ing source to produce frequencies up to 40 MHz. The
PLL is enabled by programming the FOSC<2:0>
ECPLL) or ‘100’ (for HSPLL). In addition, the PLLEN bit
(OSCTUNE<6>) must also be set. Clearing PLLEN
configuration. It also allows additional flexibility for
FIGURE 3-5:
HSPLL or ECPLL (CONFIG2L)
OSC2
OSC1
PLL Enable (OSCTUNE)
HS or EC
PLL FREQUENCY MULTIPLIER
Mode
F
F
IN
OUT
4
PLL BLOCK DIAGRAM
 2010 Microchip Technology Inc.
Comparator
Loop
Filter
Phase
VCO
SYSCLK