STM32F100RET6B STMicroelectronics, STM32F100RET6B Datasheet - Page 74

• Manufacturer Part Number: STM32F100RET6B
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F100RET6B

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical characteristics
5.3.15
74/97
Figure 27. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 46.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 28. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
the series resistance must be minimum
Table
hys(NRST)
R
PU
46. Otherwise the reset will not be taken into account by the device.
9.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
EXT ERNAL
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) ≤ 2/3)T and if the duty cycle is (45-55%)
Table
43).
Parameter
t r(I O)out
Doc ID 15081 Rev 5
(~10% order)
10%
50%
when loaded by 50pF
90%
.
(2)
STM32F100xC, STM32F100xD, STM32F100xE
Conditions
V
DD
IN
T
10%
=
supply voltage conditions summarized
Table 46
V
SS
50%
90%
t r(I O)out
–0.5
Min
300
30
2
are derived from tests
IL(NRST)
max level specified in
Typ
200
40
V
DD
Max
100
0.8
50
+0.5
ai14131
Unit
to
mV
kΩ
ns
ns
V