SAA7154E/V2/G,518 NXP Semiconductors, SAA7154E/V2/G,518 Datasheet - Page 35

• Manufacturer Part Number: SAA7154E/V2/G,518
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G,518

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
7.14.3 Clock and real-time synchronization signals at the RT-port
Table 9.
[1]
The generation of the line-locked video clock LLC (pixel clock) and of the frame-locked
audio serial bit clock requires a crystal accurate frequency reference. An oscillator is
built-in for fundamental or third harmonic crystals (the SAA7154E; SAA7154H supports
crystals with 32.11 MHz or 24.576 MHz). Alternatively, pin XTALI can be driven from an
external single-ended oscillator.
The crystal oscillation can propagate as a clock to other ICs in the system through
pin XTOUT.
The Line-Locked Clock (LLC) is the double pixel clock of the nominal 27 MHz in case of
SDTV signals (pixel clock for HDTV). It is locked to the selected video input, generating
baseband video pixel according to ITU recommendation 601 . In order to support
interfacing circuits, a direct pixel clock (LLC2) for SDTV-signals is also provided.
The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various
real-time status information can be selected for the RTS pins. The signals are always
available (output) and reflect the synchronization operation of the decoder part in the
SAA7154E; SAA7154H.
Table 10.
Pin
AMCLK
AMXCLK I
ASCLK
ALRCLK
Pin
Crystal oscillator
XTALI
XTALO
XTOUT
Real-time signals (RT-port)
LLC
LLC2_54 O
See
Table
I/O
O
O
O
I/O
I
O
O
O
Audio clock pin description
Clock and real-time synchronization signals
[1]
4.
Description
audio master clock output
external audio master clock input for the clock division
circuit; can be directly connected to output AMCLK for
standard applications
serial audio clock output; can be synchronized to rising
or falling edge of AMXCLK
audio channel (left/right) clock output; can be
synchronized to rising or falling edge of ASCLK
Description
input for crystal oscillator or reference clock
output of crystal oscillator
reference (crystal) clock output drive (optional)
line-locked clock, nominal 27 MHz, double pixel clock
locked to the selected video input signal (pixel clock in
case of HDTV)
line-locked pixel clock, nominal 13.5 MHz; or ADC clock
54 MHz; selectable through I
Rev. 02 — 6 December 2007
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
2
C-bus
Control through
ACPF[17:0] and
ACNI[21:0]
-
SDIV[5:0] and SCPH
LRDIV[5:0] and
LRPH
Control through
-
-
XTOUTE
-
SLLC2
© NXP B.V. 2007. All rights reserved.
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