SAA7154E/V2/G,518 NXP Semiconductors, SAA7154E/V2/G,518 Datasheet - Page 56
SAA7154E/V2/G,518
Manufacturer Part Number
SAA7154E/V2/G,518
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7154EV2G518.pdf
(90 pages)
Specifications of SAA7154E/V2/G,518
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
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Table 27.
Table 28.
Extended register function
Unused lower range of previous field
Unused lower range of previous field,
Unused upper range of previous field
Flags
Line selector for maximum value
capturing result
Line selector for maximum value
capturing result, sync level
Sync level
Sync amplitude
Black level, sync amplitude
Black level, burst amplitude
Burst amplitude, digital clamp value
Digital clamp value
Digital gain value
Digital gain value, gain correction value 4Ch
Gain correction value
Noise on horizontal sync, DC-values on
input detection ADCs Input Source
Detection ISD1 and ISD2
Level on FSW / L4 -input DC-values on
input detection ADC ISD3
Extended register function
Gravity 11
Gravity 12
Gravity 13
Gravity 21
Gravity 22
Gravity 23
Gravity 31
Registers 40h to 4Fh used by Analog Input Control (AIC) expert mode status (read only)
Registers 50h to 59h used by color improvement (gravity functions)
Subaddress D7
50h
51h
52h
53h
54h
55h
56h
Subaddress D7
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Dh
4Eh
4Fh
GR_EN1
GR_U_CENTER1[7:0]
GR_V_CENTER1[7:0]
GR_EN2
GR_U_CENTER2[7:0]
GR_V_CENTER2[7:0]
GR_EN3
FLD_LOWER_GAP[7:0]
FLD_UPPER_GAP[5:0]
reserved
LNSL_UPPER_GAP[7:0]
SYNC_LVL[5:0]
reserved
SYNC_AMP[7:0]
BLACK_LVL[5:0]
BURST_AMP[3:0]
FINE_CLMP[1:0]
FINE_CLMP[9:2]
FINE_GAIN[7:0]
WIPA_CORR[4:0]
reserved
HNOISE
DCS4
D6
0
0
0
D6
reserved
reserved
D5
GR_UV_FORCE1[1:0]
GR_UV_FORCE2[1:0]
GR_UV_FORCE3[1:0]
D5
LUM_UND
ERRANGE
BURST_AMP[9:4]
WIPA_CORR[10:5]
DCS2[2:0]
D4
D4
LUM_OVE
RRANGE
D3
0
0
0
D3
FLD_UPPER_GAP[9:6]
SYNC_LVL[9:6]
BLACK_LVL[9:6]
D2
GR_UV_RANGE1[2:0]
GR_UV_RANGE2[2:0]
GR_UV_RANGE3[2:0]
D2
FINE_GAIN[10:8]
DCS1[2:0]
DCS3[2:0]
D1
D1
FLD_LOWER_GAP[9:8]
LNSL_UPPER_GAP[9:8]
SYNC_AMP[9:8]
D0
D0
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